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Methods for avoiding parasitic capacitance in an integrated circuit package

DC CAFC
  • US 8,288,269 B2
  • Filed: 10/04/2011
  • Issued: 10/16/2012
  • Est. Priority Date: 03/22/2006
  • Status: Active Grant
First Claim
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1. A method, comprising steps of:

  • forming a first electrically conductive layer including a plurality of rows of contact pads;

    forming an electrically insulating layer on the first electrically conductive layer; and

    forming a second electrically conductive layer over the electrically insulating layer such that there is no intermediate conductive layer between the first and second electrically conductive layers, the second electrically conductive layer comprising metal and a plurality of cutouts wherein each cutout encloses an electrically insulating area within the second electrically conductive layer and wherein each electrically insulating area completely overlaps a corresponding one of the contact pads such that there is substantially no overlap of the rows of contact pads with metal in the second electrically conductive layer.

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