Gate structure of semiconductor device having a conductive structure with a middle portion and two spacer portions

• US 8,288,815 B2
• Filed: 12/12/2008
• Issued: 10/16/2012
• Est. Priority Date: 12/12/2008
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh-Kun, Lue, Hang-Ting
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US12/333,359
• Publication Number:
  US 20100148239A1
• Time in Patent Office: 1,404 Days
• Field of Search: 257/324, 257/E29.309
• US Class Current: 257/324
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfaces. The first surface is between the two second surfaces. The two spacer portions are respectively connected to the two second surfaces of the middle portion. A width of each of the two spacer portions gradually increases from top to bottom.

Claims

1. A gate structure for a semiconductor device, the gate structure comprising:

a conductive structure disposed over a substrate, the conductive structure comprising;

a middle portion having a first surface and two second surfaces, wherein the first surface is between the two second surfaces; and

two conductive spacer portions respectively connected to the two second surfaces of the middle portion, wherein a width of each of the two conductive spacer portions gradually increases from top to bottom, wherein an inner surface of each of the two conductive spacer portions contacts with the middle portion, and an outer surface of each of the two conductive spacer portions opposite the inner surface of each of the two conductive spacer portions is a curved surface; and

a mask layer disposed on the middle portion of the conductive structure, wherein two sides of the mask layer are respectively enclosed by the two conductive spacer portions of the conductive structure so that the mask layer is embedded into the conductive structure.

2. The gate structure according to claim 1, wherein the semiconductor device comprises a dielectric layer disposed on the substrate, the conductive structure is disposed on the dielectric layer, and the dielectric layer comprises a charge trapping layer for storing charges.

3. The gate structure according to claim 2, wherein the dielectric layer further comprises at least one of a tunneling layer and a blocking layer, the tunneling layer is disposed between the substrate and the charge trapping layer, and the blocking layer is disposed between the charge trapping layer and the conductive structure.

12. The gate structure according to claim 1, wherein the mask layer comprises silicon oxide or silicon nitride.

4. A semiconductor device, comprising:

a substrate;

a dielectric layer formed on the substrate; and

a plurality of gate structures, each of which comprises;

a conductive structure disposed over the dielectric layer, wherein the conductive structure comprises a middle portion and two conductive spacer portions, the middle portion has a first surface and two second surfaces, wherein the first surface is between the two second surfaces, the two conductive spacer portions are respectively connected to the two second surfaces of the middle portion, and a width of each of the two conductive spacer portions gradually increases from top to bottom, wherein an inner surface of each of the two conductive spacer portions contacts with the middle portion, and an outer surface of each of the two conductive spacer portions opposite the inner surface of each of the two conductive spacer portions is a curved surface; and

a mask layer disposed on the middle portion of the conductive structure, wherein two sides of the mask layer are respectively enclosed by the two conductive spacer portions of the conductive structure so that the mask layer is embedded into the conductive structure.

5. The semiconductor device according to claim 4, wherein the dielectric layer comprises a charge trapping layer for storing charges.

6. The semiconductor device according to claim 5, wherein the dielectric layer further comprises at least one of a tunneling layer and a blocking layer, the tunneling layer is disposed between the substrate and the charge trapping layer, and the blocking layer is disposed between the charge trapping layer and the conductive structure.

7. The semiconductor device according to claim 4, wherein when a voltage is applied to the gate structures, an inversion area is formed in the substrate between the two adjacent gate structures.

8. The semiconductor device according to claim 4, further comprising two doped regions respectively located in the substrate on two sides of each gate structure.

9. The semiconductor device according to claim 4 is a NAND array memory.

10. The semiconductor device according to claim 4 is a PACAND array memory.

11. The semiconductor device according to claim 4 is a virtual ground array memory.

13. A gate structure for a semiconductor device, the gate structure comprising:

a conductive structure disposed over a substrate, the conductive structure comprising;

a top conductive portion and a bottom conductive portion, wherein the top conductive portion is on the bottom conductive portion and the top conductive portion has a smaller width than the bottom conductive portion; and

a conductive sidewall spacer on the bottom conductive portion, the top conductive portion having a sidewall contacting the conductive sidewall spacer; and

a non-conductive layer disposed on the top conductive portion of the conductive structure, wherein a width of the non-conductive layer is greater than a width of the top conductive portion.

14. The gate structure according to claim 13, wherein the sidewall of the top conductive portion is a vertical sidewall and the bottom conductive portion has a curved sidewall.

15. The gate structure according to claim 13, wherein a top surface of the non-conductive layer and a top surface of the conductive sidewall spacer are in the same plane.

16. The gate structure according to claim 13, wherein the non-conductive layer comprises silicon oxide or silicon nitride.

17. The gate structure according to claim 13, wherein the semiconductor device comprises a dielectric layer disposed on the substrate, the conductive structure is disposed on the dielectric layer, and the dielectric layer comprises a charge trapping layer for storing charges.