Semiconductor memory device and method for manufacturing same
First Claim
1. A semiconductor memory device comprising:
- a base having a substrate and a peripheral circuit formed on the substrate;
a stacked body having a plurality of conductive layers and insulating layers stacked alternately above the base;
a memory film including a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body;
a channel body provided inside the memory film in the memory hole;
a contact plug provided by piercing the stacked body;
a global bit line provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug; and
a plurality of local bit lines provided above the stacked body and divided in an extending direction of the plurality of local bit lines, the plurality of local bit lines connected to the channel body and commonly connected to the global bit line through the contact plug.
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Accused Products
Abstract
According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines. The plurality of local bit lines are connected to the channel body and commonly connected to the global bit line through the contact plug.
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Citations
14 Claims
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1. A semiconductor memory device comprising:
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a base having a substrate and a peripheral circuit formed on the substrate; a stacked body having a plurality of conductive layers and insulating layers stacked alternately above the base; a memory film including a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body; a channel body provided inside the memory film in the memory hole; a contact plug provided by piercing the stacked body; a global bit line provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug; and a plurality of local bit lines provided above the stacked body and divided in an extending direction of the plurality of local bit lines, the plurality of local bit lines connected to the channel body and commonly connected to the global bit line through the contact plug. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for manufacturing a semiconductor memory device comprising:
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forming a peripheral circuit on a surface of a substrate; forming a global bit line above the peripheral circuit; alternately stacking a plurality of conductive layers with a plurality of insulating layers above the global bit line to form a stacked body; forming a memory hole in the stacked body; forming a memory film including a charge storage film on an inner wall of the memory hole; forming a channel body inside the memory film in the memory hole; forming a contact plug connected to the global bit line by piercing the stacked body; and forming a plurality of local bit lines above the stacked body, the plurality of local bit lines connected to the channel body and the contact plug and divided in an extending direction of the plurality of local bit lines. - View Dependent Claims (13, 14)
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Specification