Devices with nanocrystals and methods of formation

• US 8,288,818 B2
• Filed: 04/18/2011
• Issued: 10/16/2012
• Est. Priority Date: 07/20/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej S., Durcan, D. Mark
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US13/088,777
• Publication Number:
  US 20110210386A1
• Time in Patent Office: 547 Days
• Field of Search: 257/325, 257/E29.309
• US Class Current: 257/325
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: Y10S 438/962 Quantum dots and lines

Abstract

Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The creation of the nucleation sites includes implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures can be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures include at least one of nanocrystals, nanowires, and nanotubes. According to various nanocrystal embodiments, the nanocrystals are positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.

Claims

1. A non-volatile transistor comprising:

a semiconductor substrate having at least two diffused regions with a diffusion type opposite of the substrate forming a source region and a drain region;

a channel region disposed between the source region and drain region;

a dielectric layer disposed above the channel region;

ion nucleation sites embedded in a surface of the dielectric layer opposite the channel region;

a plurality of electrically isolated nanocrystals disposed upon the dielectric layer, each electrically isolated nanocrystal of the plurality disposed from a respective ion implanted material of the ion nucleation sites, the ion implanted material being of a material different from the electrically isolated nanocrystals;

an inter-gate dielectric layer disposed above the plurality of electrically isolated nanocrystals;

a control gate electrode disposed above the inter-gate dielectric layer.

2. The non-volatile transistor of claim 1, wherein the electrically isolated nanocrystals comprise a material selected from the list including platinum (Pt), rhodium (Rh), ruthenium (Ru), palladium (Pd), cobalt (Co), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), tungsten (W), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), titanium oxide (TiO_x), cobalt oxide (CoO_x), ruthenium oxide (RuO_x), hafnium oxide (HfO_x), aluminum oxide (Al₂O₃), tungsten oxide (WO_x), titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), and combinations thereof.

3. The non-volatile transistor of claim 1, wherein each electrically isolated nanocrystal is attached to the dielectric layer by its respective ion nucleation site formed by a defect including at least one material selected from the list including boron, nitrogen, neon, argon, helium, xenon, krypton, platinum, ruthenium, rhodium, palladium, titanium, zirconium, hafnium, silicon, germanium, carbon cobalt, and tantalum.

4. The non-volatile transistor of claim 1, wherein the channel region is approximately 40 nanometers in length and 40 nanometers in width, and there are approximately 100 electrically isolated nanocrystals distributed substantially evenly across the channel region.

5. The non-volatile transistor of claim 1, wherein the electrically isolated nanocrystals have a maximum diameter of 4.0 nanometers and a density greater than one nanocrystal per 20 square nanometers.

6. The non-volatile transistor of claim 1, wherein the electrically isolated nanocrystals are substantially uniformly distributed upon the dielectric layer.

7. The non-volatile transistor of claim 1, wherein the electrically isolated nanocrystals comprise metal nanocrystal, insulating nanocrystals, or combinations of metal nanocrystal and insulating nanocrystals.

8. The non-volatile transistor of claim 1, wherein the semiconductor substrate comprises amorphous silicon, polycrystalline silicon, germanium, or a compound semiconductor.

9. A flash memory comprising:

a semiconductor substrate having a plurality of structures, each structure including

a pair of diffused regions forming a source and a drain;

a channel region disposed between the source and the drain;

a dielectric layer disposed above the channel region;

ion nucleation sites embedded in a surface of the dielectric layer opposite the channel region;

a plurality of electrically isolated nanocrystals disposed upon the dielectric layer, each electrically isolated nanocrystal of the plurality disposed from a respective ion implanted material of the ion nucleation sites, the ion implanted material being of a material different from the electrically isolated nanocrystals;

an inter-gate dielectric layer disposed above the plurality of electrically isolated nanocrystals; and

a control gate electrode disposed upon the inter-gate dielectric layer above the channel regions; and

conductive signal lines interconnecting the plurality of control gate electrodes.

10. The flash memory of claim 9, wherein the electrically isolated nanocrystals comprise a material selected from the list including platinum (Pt), rhodium (Rh), ruthenium (Ru), palladium (Pd), cobalt (Co), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), tungsten (W), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), titanium oxide (TiO_x), cobalt oxide (CoO_x), ruthenium oxide (RuO_x), hafnium oxide (HfO_x), aluminum oxide (Al₂O₃), tungsten oxide (WO_x), titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), and combinations thereof.

11. The flash memory of claim 9, wherein each electrically isolated nanocrystal is attached to the dielectric layer by its respective ion nucleation site formed by a defect including at least one material selected from the list including boron, nitrogen, neon, argon, krypton, platinum, ruthenium, rhodium, palladium, titanium, zirconium, hafnium, silicon, germanium, cobalt, and tantalum.

12. The flash memory of claim 9, wherein the channel region is approximately 40 nanometers in length and 40 nanometers in width, and there are approximately 100 electrically isolated nanocrystals distributed substantially evenly across the channel region.

13. The flash memory of claim 9, wherein the electrically isolated nanocrystals of the have a maximum diameter of 4.0 nanometers and a density greater than one nanocrystal per 20 square nanometers.

14. The flash memory of claim 9, wherein the electrically isolated nanocrystals are disposed with substantially even distribution in size and spacing.

15. The flash memory of claim 9, wherein the dielectric layer comprises one of more of silicon oxide, silicon nitride, or silicon oxynitride.

16. A memory comprising:

a semiconductor substrate having at least two diffused regions with a diffusion type opposite of the substrate forming a source region and a drain region;

a channel region disposed between the source region and drain region;

a dielectric layer disposed above the channel region;

ion nucleation sites embedded in a surface of the dielectric layer opposite the channel region;

a first plurality of electrically isolated nanocrystals disposed upon the dielectric layer, each electrically isolated nanocrystal of the first plurality disposed from a respective ion implanted material of the ion nucleation sites, the ion implanted material being of a material different from the electrically isolated nanocrystals;

a first inter-gate dielectric layer disposed above the first plurality of electrically isolated nanocrystals;

a second plurality of electrically isolated nanocrystals disposed upon the first inter-gate dielectric layer;

a second inter-gate dielectric layer disposed above the second plurality of electrically isolated nanocrystals; and

a control gate electrode disposed above the second inter-gate dielectric layer.

17. The memory of claim 16, wherein the memory includes one or more pluralities of electrically isolated nanocrystals between the dielectric layer and the control gate electrode in addition to the first and second pluralities of electrically isolated nanocrystals and vertically spaced from the first and second pluralities of electrically isolated nanocrystals.

18. The flash memory of claim 16, wherein the dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, alumina, titanium dioxide, hafnium dioxide, tantalum dioxide, or barium titanate.

19. The flash memory of claim 16, wherein the electrically isolated nanocrystals of the first plurality of electrically isolated nanocrystals or the second plurality of electrically isolated nanocrystals comprises one or more of a conductive material or a semiconductor material capable of forming nanocrystals.

20. The flash memory of claim 16, wherein the electrically isolated nanocrystals of the first plurality of electrically isolated nanocrystals include oxidized nanocrystals.