Logic circuit and display device having the same
First Claim
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1. A semiconductor device comprising:
- a source follower circuit comprising an input portion, an output portion, and a bias input portion;
a logic circuit comprising an input portion electrically connected to the output portion of the source follower circuit, the logic circuit comprising a transistor;
a first wiring electrically connected to the source follower circuit, the first wiring being adapted to be supplied with a first constant low potential;
a second wiring electrically connected to the logic circuit, the second wiring being adapted to be supplied with a second constant low potential;
a third wiring electrically connected to the source follower circuit, the third wiring being adapted to be supplied with a first constant high potential; and
a fourth wiring electrically connected to the logic circuit, the fourth wiring being adapted to be supplied with a second constant high potential,wherein the first constant low potential is lower than the second constant low potential.
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Abstract
It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided.
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Citations
26 Claims
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1. A semiconductor device comprising:
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a source follower circuit comprising an input portion, an output portion, and a bias input portion; a logic circuit comprising an input portion electrically connected to the output portion of the source follower circuit, the logic circuit comprising a transistor; a first wiring electrically connected to the source follower circuit, the first wiring being adapted to be supplied with a first constant low potential; a second wiring electrically connected to the logic circuit, the second wiring being adapted to be supplied with a second constant low potential; a third wiring electrically connected to the source follower circuit, the third wiring being adapted to be supplied with a first constant high potential; and a fourth wiring electrically connected to the logic circuit, the fourth wiring being adapted to be supplied with a second constant high potential, wherein the first constant low potential is lower than the second constant low potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device comprising:
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a source follower circuit comprising an input portion, an output portion, and a bias input portion; a logic circuit comprising an input portion electrically connected to the output portion of the source follower circuit, the logic circuit comprising a plurality of transistors; a first wiring electrically connected to the source follower circuit, the first wiring being adapted to be supplied with a first constant low potential; a second wiring electrically connected to the logic circuit, the second wiring being adapted to be supplied with a second constant low potential; a third wiring electrically connected to the source follower circuit, the third wiring being adapted to be supplied with a first high potential; and a fourth wiring electrically connected to the logic circuit, the fourth wiring being adapted to be supplied with a second high potential, wherein the first constant low potential is lower than the second constant low potential. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor device comprising:
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a logic circuit comprising; an input portion, an output portion, a first transistor, a second transistor, a third transistor and a fourth transistor; one of a source and a drain of the first transistor electrically connected to a first wiring, the first wiring being adapted to be supplied with a constant high potential; a gate of the first transistor electrically connected to the input portion; one of a source and a drain of the second transistor electrically connected to the other of the source and the drain of the first transistor; the other of the source and the drain of the second transistor electrically connected to a second wiring, the second wiring being adapted to be supplied with a first constant low potential; a gate of the second transistor electrically connected to a third wiring, the third wiring being adapted to be supplied with a first constant potential; one of a source and a drain of the third transistor electrically connected to a fourth wiring, the fourth wiring being adapted to be supplied with the constant high potential; a gate of the third transistor electrically connected to a fifth wiring, the fifth wiring being adapted to be supplied with a second constant potential; one of a source and a drain of the fourth transistor electrically connected to the other of the source and the drain of the third transistor; the other of the source and the drain of the fourth transistor electrically connected to a sixth wiring, the sixth wiring being adapted to be supplied with a second constant low potential; and a gate of the fourth transistor electrically connected to a first electric node at the connection between the first transistor and the second transistor, wherein the output portion is electrically connected to a second electric node at the electric connection between the third transistor and the fourth transistor, and wherein the first constant low potential is lower than the second constant low potential. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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Specification