Logic circuit and display device having the same

• US 8,289,052 B2
• Filed: 09/30/2010
• Issued: 10/16/2012
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kawae, Daisuke
• Primary Examiner(s): Ismail, Shawki S
• Assistant Examiner(s): White, Dylan
• Application Number:
  US12/894,881
• Publication Number:
  US 20110084731A1
• Time in Patent Office: 747 Days
• Field of Search: 326 80- 83, 326 93- 95, 326/101, 326/102, 326/104, 326/112, 326/115, 326/119, 326/121
• US Class Current: 326/102
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/167 by electrophoresis
• CPC Class Codes: G02F 1/1671 involving dry toners
• CPC Class Codes: H03K 19/09407 of the same canal type

Abstract

It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided.

Claims

1. A semiconductor device comprising:

a source follower circuit comprising an input portion, an output portion, and a bias input portion;

a logic circuit comprising an input portion electrically connected to the output portion of the source follower circuit, the logic circuit comprising a transistor;

a first wiring electrically connected to the source follower circuit, the first wiring being adapted to be supplied with a first constant low potential;

a second wiring electrically connected to the logic circuit, the second wiring being adapted to be supplied with a second constant low potential;

a third wiring electrically connected to the source follower circuit, the third wiring being adapted to be supplied with a first constant high potential; and

a fourth wiring electrically connected to the logic circuit, the fourth wiring being adapted to be supplied with a second constant high potential,

wherein the first constant low potential is lower than the second constant low potential.

2. The semiconductor device according to claim 1, wherein the logic circuit is an inverter circuit.

3. The semiconductor device according to claim 1, wherein the transistor is part of a NOR circuit.

4. The semiconductor device according to claim 1, wherein the transistor is part of a NAND circuit.

5. The semiconductor device according to claim 1, wherein the transistor is an n-channel depletion transistor having a negative threshold voltage.

6. The semiconductor device according to claim 1,

wherein the transistor comprises a semiconductor layer formed using an oxide semiconductor.

7. The semiconductor device according to claim 1,

wherein the source follower circuit further comprises a transistor, a gate of the transistor and a source of the transistor being electrically connected to the bias input portion of the source follower circuit and to the first wiring, respectively.

8. The semiconductor device according to claim 7,

wherein the gate and the source of the transistor of the source follower can be at different electric potential from each other.

9. The semiconductor device according to claim 1,

the source follower circuit further comprising a transistor;

the logic circuit further comprising a bias input portion,

wherein the transistor of the source follower is electrically connected to the bias input portion of the source follower circuit, and

wherein the bias input portion of the logic circuit is electrically connected to a gate of the transistor of the logic circuit.

10. A semiconductor device comprising:

a source follower circuit comprising an input portion, an output portion, and a bias input portion;

a logic circuit comprising an input portion electrically connected to the output portion of the source follower circuit, the logic circuit comprising a plurality of transistors;

a first wiring electrically connected to the source follower circuit, the first wiring being adapted to be supplied with a first constant low potential;

a second wiring electrically connected to the logic circuit, the second wiring being adapted to be supplied with a second constant low potential;

a third wiring electrically connected to the source follower circuit, the third wiring being adapted to be supplied with a first high potential; and

a fourth wiring electrically connected to the logic circuit, the fourth wiring being adapted to be supplied with a second high potential,

wherein the first constant low potential is lower than the second constant low potential.

11. The semiconductor device according to claim 10, wherein the logic circuit is an inverter circuit.

12. The semiconductor device according to claim 10, wherein the transistors are part of a NOR circuit.

13. The semiconductor device according to claim 10, wherein the transistors are part of a NAND circuit.

14. The semiconductor device according to claim 10, wherein the plurality of transistors each are an n-channel depletion transistor comprising an oxide semiconductor and having a negative threshold voltage.

15. The semiconductor device according to claim 10,

wherein the transistors each comprise a semiconductor layer formed using an oxide semiconductor.

16. The semiconductor device according to claim 10,

wherein the source follower circuit further comprises a transistor, a gate of the transistor and a source of the transistor being electrically connected to the bias input portion of the source follower circuit and to the first wiring, respectively.

17. The semiconductor device according to claim 16,

wherein the gate and the source of the transistor of the source follower can be at different electric potential from each other.

18. The semiconductor device according to claim 10,

the source follower circuit further comprising a transistor;

the logic circuit further comprising a bias input portion,

wherein the transistor of the source follower is electrically connected to the bias input portion of the source follower circuit, and

wherein the bias input portion of the logic circuit is electrically connected to a gate of one of the transistor of the logic circuit.

19. A semiconductor device comprising:

a logic circuit comprising;

an input portion, an output portion, a first transistor, a second transistor, a third transistor and a fourth transistor;

one of a source and a drain of the first transistor electrically connected to a first wiring, the first wiring being adapted to be supplied with a constant high potential;

a gate of the first transistor electrically connected to the input portion;

one of a source and a drain of the second transistor electrically connected to the other of the source and the drain of the first transistor;

the other of the source and the drain of the second transistor electrically connected to a second wiring, the second wiring being adapted to be supplied with a first constant low potential;

a gate of the second transistor electrically connected to a third wiring, the third wiring being adapted to be supplied with a first constant potential;

one of a source and a drain of the third transistor electrically connected to a fourth wiring, the fourth wiring being adapted to be supplied with the constant high potential;

a gate of the third transistor electrically connected to a fifth wiring, the fifth wiring being adapted to be supplied with a second constant potential;

one of a source and a drain of the fourth transistor electrically connected to the other of the source and the drain of the third transistor;

the other of the source and the drain of the fourth transistor electrically connected to a sixth wiring, the sixth wiring being adapted to be supplied with a second constant low potential; and

a gate of the fourth transistor electrically connected to a first electric node at the connection between the first transistor and the second transistor,

wherein the output portion is electrically connected to a second electric node at the electric connection between the third transistor and the fourth transistor, and

wherein the first constant low potential is lower than the second constant low potential.

20. The semiconductor device according to claim 19, wherein the logic circuit is an inverter circuit.

21. The semiconductor device according to claim 19, wherein the third transistor and the fourth transistor are part of a NOR circuit.

22. The semiconductor device according to claim 19, wherein the third transistor and the fourth transistor are part of a NAND circuit.

23. The semiconductor device according to claim 19, wherein the first constant potential can be different from the second constant potential.

24. The semiconductor device according to claim 19, wherein the first constant potential and the first low potential can be different.

25. The semiconductor device according to claim 19, the first transistor, the second transistor, the third transistor and the fourth transistor each are an n-channel depletion transistor comprising an oxide semiconductor and having negative threshold voltage.

26. The semiconductor device according to claim 19,

wherein the transistors each comprise a semiconductor layer formed using an oxide semiconductor.