Gate control circuit for high bandwidth switch design

• US 8,289,066 B2
• Filed: 12/30/2009
• Issued: 10/16/2012
• Est. Priority Date: 12/30/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics Asia Pacific Pte Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Asia Pacific Pte Limited (STMicroelectronics NV)
• Inventors: Guo, Dianbo
• Primary Examiner(s): COX, CASSANDRA F
• Application Number:
  US12/650,377
• Publication Number:
  US 20110156794A1
• Time in Patent Office: 1,021 Days
• Field of Search: None
• US Class Current: 327/427
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

An analog switch configuration includes a gate control circuit coupled between an input of a switch and a gate of the switch. The gate control circuit passes voltage changes on the input of the switch to the gate of the switch to decrease the influence the inherent gate to input capacitance has on the bandwidth of the switch. By reducing the change in voltage across the inherent capacitance, the current through the capacitance in decreased as well as its influence on the bandwidth of the configuration.

Claims

1. A semiconductor circuit, comprising:

a switch including an input terminal, an output terminal, and a control terminal;

a first transistor having an output terminal coupled to the control terminal of the switch;

a second transistor having an output terminal coupled to the control terminal of the switch; and

a third transistor having a first terminal and a second terminal, the first terminal of the third transistor being coupled to the input terminal of the switch and the second terminal of the third transistor being coupled to the control terminal of the switch; and

a resistor coupled to the third transistor between the control terminal of the switch and the input of the switch, the coupling configured to pass a change in a voltage potential on the input terminal of the switch from the input terminal of the switch to the control terminal of the switch.

2. A semiconductor circuit, comprising:

a switch including an input terminal, an output terminal, and a control terminal;

a first transistor having an output terminal coupled to the control terminal of the switch;

a second transistor having an output terminal coupled to the control terminal of the switch; and

a third transistor having a first terminal and a second terminal, the first terminal of the third transistor being coupled to the input terminal of the switch and the second terminal of the third transistor being coupled to the control terminal of the switch, the coupling configured to pass a change in a voltage potential on the input terminal of the switch from the input terminal of the switch to the control terminal of the switch, wherein the first terminal of the third transistor is a gate terminal and the second terminal of the third transistor is a source terminal.

3. The semiconductor circuit of claim 2 wherein the second terminal of the third transistor is coupled to a first terminal of a resistor and a second terminal of the resistor is coupled to the control terminal of the switch.

4. The semiconductor circuit of claim 3 wherein a third terminal of the third transistor is a drain terminal, said third terminal being connected to ground.

5. A semiconductor circuit, comprising:

a switch including an input terminal, an output terminal, and a control terminal;

a first transistor having an output terminal coupled to the control terminal of the switch;

a second transistor having an output terminal coupled to the control terminal of the switch; and

a third transistor having a first terminal and a second terminal, the first terminal of the third transistor being coupled to the input terminal of the switch and the second terminal of the third transistor being coupled to the control terminal of the switch, the coupling configured to pass a change in a voltage potential on the input terminal of the switch from the input terminal of the switch to the control terminal of the switch, wherein the first terminal of the third transistor is a drain terminal and the second terminal of the third transistor is a source terminal.

6. The semiconductor circuit of claim 5 wherein the first terminal of the third transistor is coupled to a first terminal of a resistor and a second terminal of the resistor is coupled to the input terminal of the switch.

7. The semiconductor circuit of claim 6 wherein a third terminal of the third transistor is configured to enable and disable the third transistor.

8. The semiconductor circuit of claim 7 wherein the first transistor is configured to operate as a current source.

9. A semiconductor circuit, comprising:

a switch including an input terminal, an output terminal, and a gate terminal; and

a gate control circuit coupled to the gate terminal of the switch, comprising;

a first control transistor having an output terminal coupled to the gate terminal of the switch;

a second control transistor having a gate terminal and an output terminal, the output terminal of the second control transistor being coupled to the gate terminal of the switch, the gate terminal of the second control transistor configured to receive a control signal for the switch; and

a means for transferring at least part of a change in voltage potential on the input of the switch to the gate terminal of the switch, wherein said means includes a third control transistor and resistor coupled between the input terminal of the switch and the gate terminal of the switch.

10. The semiconductor circuit of claim 9 wherein the first control transistor is configured to supply a substantially fixed current.

11. The semiconductor circuit of claim 9 wherein the means for transferring maintains a substantially fixed voltage drop across it.

12. The semiconductor circuit of claim 9 wherein the first control transistor is configured as a current source.

13. A method of operating an analog switch, comprising:

receiving a voltage signal on an input of the switch;

receiving a control signal at a first transistor to enable or disable the switch;

biasing a control terminal of the switch with a second transistor coupled between the control terminal of the switch and a voltage supply; and

transferring at least part of any change in the voltage signal at the input of the switch from the input of the switch to the control terminal of the switch to decrease the affect of an inherent capacitance between the input and the control terminal of the switch, wherein transferring is performed by enabling a third transistor coupled to a resistor to conduct current between the control terminal and the input of the switch.

14. The method of claim 13 wherein transferring includes supplying a substantially constant current through the third transistor and preventing the input of the switch from receiving the supplied current.