Signal processor comprising an amplifier

• US 8,289,077 B2
• Filed: 11/07/2008
• Issued: 10/16/2012
• Est. Priority Date: 11/12/2007
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Bruin, Paulus P. F. M.
• Primary Examiner(s): Mottola, Steven J
• Application Number:
  US12/742,289
• Publication Number:
  US 20100253432A1
• Time in Patent Office: 1,439 Days
• Field of Search: 330/253, 330/258, 330/260
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45498 the CSC comprising only resistors
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel

Abstract

An amplifier (A1) within a signal processor comprises a pair of complementary differential pairs (DP1, DP2) in the sense that one differential pair comprises transistors having a polarity opposite to that of transistors in the other differential pair. The one and the other differential pair commonly receive a differential input signal, which has a common mode component. A current combining circuit (CC) combines output currents of the one and the other differential pair so as to obtain an output current that varies as a function of the differential input signal. The one and the other differential pair each have a biasing circuit (R1, R2), which provides a tail current that varies with the common mode component in a substantially linear fashion.

Claims

1. A signal processor comprising an amplifier comprising:

a pair of complementary differential pairs such that one differential pair comprises transistors having a polarity opposite to that of transistors in the other differential pair, the one and the other differential pair being coupled to commonly receive a differential input signal, which has a common mode component; and

a current combining circuit arranged to combine output currents of the one and the other differential pair so as to obtain an output current that varies as a function of the differential input signal,

the one and the other differential pair being each provided with a biasing circuit for providing a tail current that varies with the common mode component in a substantially linear fashion,

the current combining circuit comprising;

a pair of current-inverting buffers, each current-inverting buffer comprising an input node that is coupled to a first supply voltage line via a biasing circuit for applying a bias current to the input node, one and the other current-inverting buffer being coupled to receive an output current and a complementary output current, respectively, of one differential pair at their respective input nodes;

a current mirror for mirroring an output current of one current-inverting buffer, the current mirror comprising an input branch and an output branch, each branch including a transistor having a main terminal that is coupled to a second supply voltage line via an impedance, the input branch and the output branch being coupled to receive an output current and a complementary output current, respectively, of the other differential pair at the respective main terminals of the respective transistors, wherein the gate terminal of the transistor included in the input branch of the current mirror is coupled to the drain terminal of the transistor included in the input branch of the current mirror; and

an output node coupled to receive an output current of the other current-inverting buffer and coupled to receive an output current of the current mirror,

the amplifier being provided with a feedback circuit so that the differential input signal represents a difference between an input signal and an output signal of the amplifier.

2. A signal processor according to claim 1 whereby, in each differential pair, the biasing circuit that provides the tail current is a resistance.

3. A signal processor according to claim 1 whereby, in each aforementioned current-inverting buffer, the biasing circuit that applies the bias current to the input node is a resistance.

4. A signal processor according to claim 1, wherein each aforementioned current-inverting buffer comprises a transistor having a control terminal coupled to receive a bias voltage and a main terminal that constitutes the input node of the current-inverting buffer.

5. A signal processor according to claim 1, wherein the transistors are of CMOS type.

6. A signal rendering system comprising a signal source and a signal processor according to claim 1 for processing an input signal that the signal source provides so as to obtain an output signal that can be applied to a signal transducer.

7. The signal processor of claim 1, wherein the gate terminal of the transistor included in the input branch of the current mirror is directly coupled to the drain terminal of the transistor included in the input branch of the current mirror.

8. The signal processor of claim 1, wherein the signal processor further comprises:

an analog-to-digital converter connected to an output terminal of the amplifier;

a digital signal processor connected to an output terminal of the analog-to-digital converter;

a digital to analog converter connected to an output terminal of the digital signal processor; and

an output amplifier connected to an output terminal of the digital to analog converter.

9. The signal processor of claim 8, wherein the signal processor further comprises a second amplifier located in a signal path that is in parallel to the amplifier, and wherein the analog-to-digital converter is connected to an output terminal of the second amplifier.

10. The signal processor of claim 9, wherein the amplifier is a voltage follower, and wherein the second amplifier is an inverting amplifier.

11. The signal processor of claim 9, wherein output signals of the amplifier and the second amplifier constitute a differential input signal for the analog-to-digital converter.

12. The signal rendering system of claim 6, wherein the signal source includes a microphone, and wherein the signal transducer includes a loudspeaker.

13. A cellular phone comprising the signal processor of claim 1.

14. A signal rendering system comprising a signal source and a signal processor for processing an input signal that the signal source provides so as to obtain an output signal that can be applied to a signal transducer, wherein the signal processor comprises an amplifier comprising:

a pair of complementary differential pairs such that one differential pair comprises transistors having a polarity opposite to that of transistors in the other differential pair, the one and the other differential pair being coupled to commonly receive a differential input signal, which has a common mode component; and

a current combining circuit arranged to combine output currents of the one and the other differential pair so as to obtain an output current that varies as a function of the differential input signal,

the one and the other differential pair being each provided with a biasing circuit for providing a tail current that varies with the common mode component in a substantially linear fashion,

the current combining circuit comprising;

a pair of current-inverting buffers, each current-inverting buffer comprising an input node that is coupled to a first supply voltage line via a biasing circuit for applying a bias current to the input node, one and the other current-inverting buffer being coupled to receive an output current and a complementary output current, respectively, of one differential pair at their respective input nodes;

a current mirror for mirroring an output current of one current-inverting buffer, the current mirror comprising an input branch and an output branch, each branch including a transistor having a main terminal that is coupled to a second supply voltage line via an impedance, the input branch and the output branch being coupled to receive an output current and a complementary output current, respectively, of the other differential pair at the respective main terminals of the respective transistors, wherein the gate terminal of the transistor included in the input branch of the current mirror is coupled to the drain terminal of the transistor included in the input branch of the current mirror; and

an output node coupled to receive an output current of the other current-inverting buffer and coupled to receive an output current of the current mirror.

15. The signal rendering system of claim 14, wherein the signal source includes a microphone, and wherein the signal transducer includes a loudspeaker.

16. A signal processor comprising an amplifier comprising:

a pair of complementary differential pairs such that one differential pair comprises transistors having a polarity opposite to that of transistors in the other differential pair, the one and the other differential pair being coupled to commonly receive a differential input signal, which has a common mode component; and

a current combining circuit arranged to combine output currents of the one and the other differential pair so as to obtain an output current that varies as a function of the differential input signal,

the one and the other differential pair being each provided with a biasing circuit for providing a tail current that varies with the common mode component in a substantially linear fashion,

the current combining circuit comprising;

a pair of current-inverting buffers, each current-inverting buffer comprising an input node that is coupled to a first supply voltage line via a biasing circuit for applying a bias current to the input node, one and the other current-inverting buffer being coupled to receive an output current and a complementary output current, respectively, of one differential pair at their respective input nodes;

a current mirror for mirroring an output current of one current-inverting buffer, the current mirror comprising an input branch and an output branch, each branch including a transistor having a main terminal that is coupled to a second supply voltage line via an impedance, the input branch and the output branch being coupled to receive an output current and a complementary output current, respectively, of the other differential pair at the respective main terminals of the respective transistors, wherein the gate terminal of the transistor included in the input branch of the current mirror is coupled to the drain terminal of the transistor included in the input branch of the current mirror; and

an output node coupled to receive an output current of the other current-inverting buffer and coupled to receive an output current of the current mirror,

wherein the signal processor further comprises;

an analog-to-digital converter connected to an output terminal of the amplifier;

a digital signal processor connected to an output terminal of the analog-to-digital converter;

a digital to analog converter connected to an output terminal of the digital signal processor; and

an output amplifier connected to an output terminal of the digital to analog converter.

17. The signal processor of claim 16, wherein the signal processor further comprises a second amplifier located in a signal path that is in parallel to the amplifier, and wherein the analog-to-digital converter is connected to an output terminal of the second amplifier.

18. The signal processor of claim 17, wherein the amplifier is a voltage follower, and wherein the second amplifier is an inverting amplifier.

19. The signal processor of claim 17, wherein output signals of the amplifier and the second amplifier constitute a differential input signal for the analog-to-digital converter.

20. A cellular phone comprising the signal processor of claim 16.