Fractional rate resampling filter on FPGA

• US 8,289,195 B1
• Filed: 03/25/2011
• Issued: 10/16/2012
• Est. Priority Date: 03/25/2011
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Neoh, Hong Shan, Dong, Xiaofei
• Primary Examiner(s): Mai, Lam T
• Application Number:
  US13/072,592
• Time in Patent Office: 571 Days
• Field of Search: 341 50- 90, 375/350, 375/229, 375/377, 375/346, 375/285, 375/240.1, 375/240.29, 702/66, 702/76, 716/100, 716/106, 708/313, 327/156, 327/291, 327/294, 327/337, 331/45, 331/46, 342/118
• US Class Current: 341/61
• CPC Class Codes: H03H 17/0292 Time multiplexed filters; Time sharing filters
• CPC Class Codes: H03H 17/0685 the ratio being rational
• CPC Class Codes: H03H 2218/08 Resource sharing

Abstract

A programmable logic device can be configured as a fractional rate resampling filter capable of performing downsampling prior to upsampling without modifying the overall filter response. Input data may be received at a first sample rate and may be downsampled to generate downsampled data. Portions of the downsampled data may be respectively output to different filtering paths. Each filtering path may include a cluster of filter components that corresponds to different subfilters of the overall filter response and may be operable to receive and process the different portions of the downsampled data. Outputs of each cluster may be combined to generate output data at a second sample rate. The resampling filter structure can reduce the number of multiplier circuits used by allowing time-division multiplexing among different filter components.

Claims

1. A method for resampling data, the method comprising:

downsampling, using commutator circuitry, input data received at a first sample rate to generate downsampled data and to output first and second portions of the downsampled data to first and second filtering paths respectively, wherein;

each filtering path includes a cluster of filter components;

a first portion of each cluster is operable to receive and process, during a first cycle, one of the first and second portions of the downsampled data; and

a second portion of each cluster is operable to receive and process, during a second cycle, the portion of the downsampled data received by the first portion of the cluster; and

combining outputs of each cluster of the first and second filtering paths to generate output data at a second sample rate.

2. The method of claim 1, wherein:

the first portion of each cluster of the first and second filtering paths respectively processes a first subband of the first and second portions of the downsampled data; and

the second portion of each cluster of the first and second filtering paths respectively processes a second subband of the first and second portions of the downsampled data.

3. The method of claim 1, wherein the combining comprises upsampling the outputs of each cluster of the first and second filtering paths following the downsampling.

4. The method of claim 3, wherein the combining comprises:

summing outputs of the first portion of each cluster of the first and second filtering paths to generate a first output;

summing outputs of the second portion of each cluster of the first and second filtering paths to generate a second output; and

selectively outputting, using selection circuitry, one of the first and second outputs at the second sample rate.

5. The method of claim 1, wherein the first and second portions of each cluster are operable to share resources, wherein the first portion of each cluster uses the resources during the first cycle, and wherein the second portion of each cluster uses the resources during the second cycle.

6. The method of claim 5, wherein the shared resources comprise a plurality of multiplier circuits and a selection circuitry associated with each multiplier circuit.

7. The method of claim 6, wherein the downsampling comprises selectively outputting to each multiplier circuit, using the selection circuitry associated with the corresponding multiplier circuit, one of a first and second filtering coefficients associated respectively with one of the first and second portions of each cluster, wherein:

the first filtering coefficient is selected during the first cycle; and

the second filtering coefficient is selected during the second cycle.

8. The method of claim 7, wherein the downsampling comprises:

delaying one of the first and second portion of downsampled data to generate a delayed portion; and

outputting the delayed portion of downsampled data into one of the multiplier circuits for multiplying with one of the first and second filtering coefficients.

9. The method of claim 6, wherein the combining comprises summing outputs of the multiplier circuits.

10. The method of claim 1, wherein the commutator circuitry comprises a low-voltage differential signaling (LVDS) receiver implemented on a field-programmable gate array (FPGA).

11. An integrated circuit for resampling data comprising:

receiver circuitry operable to downsample input data received at a first sample rate to generate downsampled data and to output first and second portions of the downsampled data to first and second filtering paths respectively, wherein;

each filtering path includes a cluster of filter components;

a first portion of each cluster is operable to receive and process, during a first cycle, one of the first and second portions of the downsampled data; and

a second portion of each cluster is operable to receive and process, during a second cycle, the portion of the downsampled data received by the first portion of the cluster; and

circuitry operable to combine outputs of each cluster of the first and second filtering paths to generate output data at a second sample rate.

12. The integrated circuit of claim 11, wherein:

the first portion of each cluster of the first and second filtering paths respectively processes a first subband of the first and second portions of the downsampled data; and

the second portion of each cluster of the first and second filtering paths respectively processes a second subband of the first and second portions of the downsampled data.

13. The integrated circuit of claim 11, wherein the circuitry operable to combine outputs of each cluster upsamples the outputs of each cluster of the first and second filtering paths following the downsampling.

14. The integrated circuit of claim 13, wherein the circuitry operable to combine outputs of each cluster comprises:

first adder circuitry operable to sum outputs of the first portion of each cluster of the first and second filtering paths to generate a first output;

second adder circuitry operable to sum outputs of the second portion of each cluster of the first and second filtering paths to generate a second output; and

selection circuitry operable to selectively output one of the first and second outputs at the second sample rate.

15. The integrated circuit of claim 11, wherein the first and second portions of each cluster are operable to share resources, wherein the first portion of each cluster uses the resources during the first cycle, and wherein the second portion of each cluster uses the resources during the second cycle.

16. The integrated circuit of claim 15, wherein the shared resources comprise a plurality of multiplier circuits and a selection circuitry associated with each multiplier circuit.

17. The integrated circuit of claim 16, wherein each cluster comprises selection circuitry associated with a corresponding multiplier circuit and operable to selectively output to the corresponding multiplier circuit one of a first and second filtering coefficients associated respectively with one of the first and second portions of the cluster, wherein:

the first filtering coefficient is selected during the first cycle; and

the second filtering coefficient is selected during the second cycle.

18. The integrated circuit of claim 17, wherein the cluster comprises delay circuitry operable to:

delay one of the first and second portion of downsampled data to generate a delayed portion; and

output the delayed portion of downsampled data into one of the multiplier circuits for multiplying with one of the first and second filtering coefficients.

19. The integrated circuit of claim 16, wherein the circuitry operable to combine outputs of each cluster comprises adder circuitry for summing outputs of the multiplier circuits.

20. The integrated circuit of claim 11, wherein the receiver circuitry comprises a low-voltage differential signaling (LVDS) receiver implemented on a field-programmable gate array (FPGA).

21. A fractional rate resampling filter comprising:

commutator circuitry having an input for downsampling data received at an input sample rate and outputting a plurality of D portions of downsampled data to a plurality of D filtering paths, wherein;

each filtering path includes a cluster of filter components with a plurality of U portions, and wherein each one of the U portions is operable to receive and process, during a respective cycle, one portion of the plurality of D portions of the downsampled data, and wherein outputs of each cluster of the plurality of D filtering paths are combined to generate output data at a fraction U/D of the input sample rate.

22. The fractional rate resampling filter of claim 21, wherein the plurality of U portions of each cluster is operable to share a plurality of multiplier circuits and a selection circuitry associated with each multiplier circuit.

23. The fractional rate resampling filter of claim 22, wherein one cluster comprises delay circuitry operable to:

delay one of the plurality of D portions of downsampled data to generate a delayed portion; and

output the delayed portion of downsampled data into one of the plurality of multiplier circuits for multiplying with one of one of U filtering coefficients associated respectively with one of the plurality of U portions of each cluster.

24. The fractional rate resampling filter of claim 21, wherein the commutator circuitry comprises a low-voltage differential signaling (LVDS) receiver implemented on a field-programmable gate array (FPGA).