Method for performing computations using wide operands

• US 8,289,335 B2
• Filed: 02/03/2006
• Issued: 10/16/2012
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Hansen, Craig, Moussouris, John, Massalin, Alexia
• Primary Examiner(s): WASHBURN, DANIEL C
• Application Number:
  US11/346,213
• Publication Number:
  US 20090083498A1
• Time in Patent Office: 2,447 Days
• Field of Search: 345/522, 712/210, 712/24, 712/28, 712/1, 712/225
• US Class Current: 345/522
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 : comprising data of variable length
• CPC Class Codes: G06F 9/30145 : Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30149 : of variable length instructions
• CPC Class Codes: G06F 9/3016 : Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 : of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/35 : Indirect addressing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4484 : Executing subprograms
• CPC Class Codes: G06F 9/45533 : Hypervisors; Virtual machine monitors
• CPC Class Codes: H03M 13/158 : Finite field arithmetic processing
• CPC Class Codes: H03M 13/4169 : using traceback H03M13/4192 takes precedence
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Claims

1. A computer processor for processing multiple threads of execution in parallel, the processor having a dedicated portion in which units of the processor are assigned to a single thread of execution, and having a shared portion in which units of the processor are shared among a plurality of threads of execution, the processor comprising:

a shared memory;

the dedicated portion of the processor having units dedicated to a thread of execution on a thread-by-thread basis, the dedicated portion of the processor including;

a first access unit dedicated to process a first thread of execution, the first access unit including (i) a first access instruction fetch queue unit for fetching instructions from the shared memory, and (ii) a first access functional unit operable (a) to compute program control flow by performing arithmetic and branch instructions, and (b) to access memory by performing load and store instructions; and

a second access unit, operating simultaneously with the first access unit, the second access unit dedicated to process a second thread of execution, the second access unit including (i) a second access instruction fetch queue unit for fetching instructions from the shared memory, and (ii) second access functional unit operable (a) to compute program control flow by performing arithmetic and branch instructions, and (b) to access memory by performing load and store instructions;

a first execution queue unit coupled to the shared memory and storing instructions and data for the first thread of execution;

a second execution queue unit coupled to the shared memory and storing instructions and data for the second thread of execution;

the shared portion of the processor having units shared by at least two of the multiple threads of execution, the shared portion of the processor including;

a plurality of execution functional units collectively operable to perform instructions not performed by the access units; and

an arbitration unit coupled to the plurality of execution functional units and to the first execution queue unit and the second execution queue unit, the arbitration unit operable on an instruction-by-instruction basis to assign instructions from the first thread of execution and the second thread of execution among the plurality of execution functional units based upon the type of instruction being executed, wherein an execution functional unit may perform instructions from either the first thread of execution or the second thread of execution based upon the operation of the arbitration unit.

2. A processor as in claim 1 wherein the plurality of execution functional units comprise a switch unit for performing data handling operations.

3. A processor as in claim 1 wherein the plurality of execution functional units comprise a switch unit for performing data handling operations.

4. A processor as in claim 3 wherein the switch unit comprises a crossbar switch.

5. A processor as in claim 1 wherein the plurality of execution functional units comprise a translate unit for performing translate operations.

6. A processor as in claim 5 wherein the translate unit performs table look up operations.

7. A processor as in claim 1 wherein each of the plurality of functional units is operable to perform only a limited class of instructions.

8. A processor as in claim 1 formed as a single integrated circuit.

9. A processor as in claim 8 wherein the shared memory is coupled through a bus interface to an external main memory not on the single integrated circuit.

10. A processor as in claim 1 wherein the first access unit and the second access unit function independently for different threads of execution.

11. A processor as in claim 1 wherein data fetched from the shared memory in response to the addresses provided by the first access unit is supplied along with instructions not performed by the first access unit and-provided to one of the execution functional units.

12. A processor as in claim 1 further comprising a first execution register file and a second execution register file, each which receive data from the first execution queue unit and supply data to the execution functional units.

13. A processor as in claim 1 further comprising:

a first data path having a first bit width coupled to the shared memory;

a second data path having a second bit width greater than the first bit width;

a plurality of third data paths having a combined bit width less than the second bit width;

a wide operand storage coupled to the first data path and to the second data path for storing a wide operand received over the first data path, the wide operand having a size with a number of bits greater than the first bit width; and

wherein the first access unit is coupled to the first data path and the third data paths, and includes storage for a wide operand specifier which specifies a memory address of a wide operand.

14. A processor as in claim 13 wherein the wide operand specifier also includes information about size of the wide operand.

15. A processor as in claim 13 wherein an execution functional unit after execution of an instruction requiring information from the wide operand storage checks an access unit when a subsequent instruction requires a wide operand to determine if the wide operand required is already stored in the wide operand storage.

16. A processor as in claim 1 wherein operation of the arbitration unit is overlapped with operation of the first and second execution queue units to reduce arbitration delays.