MRAM diode array and access method
First Claim
1. A memory unit comprising:
- a magnetic tunnel junction data cell electrically coupled to a bit line and a source line, the magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell;
a first diode electrically between the magnetic tunnel junction data cell and the source line; and
a second diode electrically between the magnetic tunnel junction data cell and the source line, the first diode and second diode in parallel electrical connection, and having opposing forward bias directionswherein the source line and bit line is precharged to a specified precharge voltage level in a range from 40 to 60% of a write voltage, the precharge voltage level being less than a threshold voltage of the first diode and second diode.
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Accused Products
Abstract
A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
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Citations
18 Claims
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1. A memory unit comprising:
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a magnetic tunnel junction data cell electrically coupled to a bit line and a source line, the magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell; a first diode electrically between the magnetic tunnel junction data cell and the source line; and a second diode electrically between the magnetic tunnel junction data cell and the source line, the first diode and second diode in parallel electrical connection, and having opposing forward bias directions wherein the source line and bit line is precharged to a specified precharge voltage level in a range from 40 to 60% of a write voltage, the precharge voltage level being less than a threshold voltage of the first diode and second diode. - View Dependent Claims (2, 3, 4, 5)
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6. A memory array, comprising:
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a plurality of bit lines; a plurality of source lines intersecting with the plurality of bit lines and forming a cross-point array; a memory unit adjacent to at least selected cross-points of the cross-point array, the memory unit comprising; a magnetic tunnel junction data cell electrically coupled to a bit line and a source line, the magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell; a first diode electrically between the magnetic tunnel junction data cell and the source line; and a second diode electrically between the magnetic tunnel junction data cell and the source line, the first diode and second diode in parallel electrical connection, and having opposing forward bias directions; wherein the memory array is precharged to a specified precharge voltage level in a range from 40 to 60% of a write voltage, the precharge voltage level being less than a threshold voltage of the first diode and second diode. - View Dependent Claims (7, 8, 9, 10)
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11. A method comprising:
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precharging a plurality of magnetic tunnel junction data cells to a specified precharge voltage level in a range from 40 to 60% of a write voltage, each magnetic tunnel junction data cell includes a first diode and a second diode in parallel electrical connection and having opposing forward bias directions, the precharge voltage being less than a threshold voltage of the first diode and second diode; switching a magnetic tunnel junction data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction, the write current provided by a first diode being electrically coupled to the magnetic tunnel junction data cell and a source line; and switching the magnetic tunnel junction data cell from a low resistance state to a high resistance state by passing a write current through the magnetic tunnel junction data cell in a second direction opposing the first direction, the write current provided by a second diode being electrically coupled to the magnetic tunnel junction data cell and a source line and in parallel electrical connection with the first diode. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification