Non-volatile memory bank and page buffer therefor

• US 8,289,805 B2
• Filed: 09/10/2010
• Issued: 10/16/2012
• Est. Priority Date: 11/27/2006
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Nguyen, VanThu
• Application Number:
  US12/879,566
• Publication Number:
  US 20110013455A1
• Time in Patent Office: 767 Days
• Field of Search: 365/185.11 X, 365/185.13 X, 365/189.011, 365/189.05 X, 365/230.08 O, 365/185.11, 365/185.13, 365/189.05, 365/230.08
• US Class Current: 365/230.08
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1048 : Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/12 : Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Claims

1. A memory bank comprising:

a first memory sector having memory cells connected to first bitlines and first wordlines, the first bitlines being arranged as m segments where m is an integer value greater than 0;

a second memory sector having memory cells connected to second bitlines and second wordlines, the second bitlines being arranged as m segments;

a page buffer disposed between the first memory sector and the second memory sector for selectively coupling one of the first bitlines and the second bitlines of each of the m segments to a predetermined number of datelines.

2. The memory bank of claim 1, wherein a read operation is executed by

activating a wordline of one of the first wordlines in the first memory sector and the second wordlines in the second memory sector in response to a row address, at least two memory cells being coupled to the first bitlines when the wordline is one of the first wordlines, and at least two memory cells being coupled to the second bitlines when the wordline is one of the second wordlines,

selectively coupling one bitline of the first bitlines and the second bitlines to a common bitline in response to a column address,

sensing the common bitline with the page buffer, and

providing data corresponding to the sensed common bitline onto one of the predetermined number of datelines.

16. The memory bank of claim 1, further including common bitlines coupled to the page buffer, each of the common bitlines coupled to at least one segment of the first bitlines and to at least one segment of the second bitlines.

17. The memory bank of claim 16, wherein the first bitlines includes a group of first segments, and the second bitlines includes a group of second segments.

18. The memory bank of claim 17, wherein

the first memory sector includes a first bitline selection circuit for selectively connecting one first segment of the group of first segments to a common bitline of the common bitlines, and

the second memory sector includes a second bitline selection circuit for selectively connecting one second segment of the group of second segments to the common bitline of the common bitlines.

19. The memory bank of claim 16, wherein the common bitlines are grouped as a first set of common bitlines and a second set of common bitlines.

20. The memory bank of claim 19, wherein the page buffer includes

a first self-decoding page buffer stage for sensing data from the first set of common bitlines, and for providing sensed data corresponding to each of the common bitlines of the first set of common bitlines on the predetermined number of data lines in response to an active column select bit latched in a clock signal state;

and,

a second self-decoding page buffer stage for sensing data from the second set of common bitlines, and for providing sensed data corresponding to each of the common bitlines of the second set of common bitlines on the predetermined number of data lines in response to the active column select bit latched in a subsequent clock signal state.

21. The memory bank of claim 20, wherein the first self-decoding page buffer stage includes an output terminal for providing the active column select bit to an input terminal of the second self-decoding page buffer stage.

22. The memory bank of claim 21, wherein the first self-decoding page buffer stage includes

a first segment page buffer for sensing data from the first set of common bitlines and providing the sensed data corresponding to each of the common bitlines of the first set of common bitlines on the corresponding data lines in response to a first enabling signal, and

a first sequential enabler receiving and latching the active column select bit and including the output terminal, the first sequential enabler providing in response to the active column select bit being latched in the clock signal state

the first enabling signal and

the active column select bit from the output terminal.

23. The memory bank of claim 22, wherein the second self-decoding page buffer stage includes

a second segment page buffer for sensing data from the second set of common bitlines and providing the sensed data corresponding to each of the common bitlines of the second set of common bitlines on the corresponding data lines in response to a second enabling signal, and

a second sequential enabler including the input terminal for receiving and latching the active column select bit provided by the first sequential enabler, the second sequential enabler providing in response to the active column select bit being latched in the subsequent clock signal state

the second enabling signal.

3. A page buffer for a memory bank comprising:

a first self-decoding page buffer stage for sensing data from a first bitline, and for providing sensed data corresponding to the first bitline on a corresponding data line in response to an active column select bit latched in a clock signal state, the first self-decoding page buffer stage including an output terminal for providing the active column select bit; and

,

a second self-decoding page buffer stage having an input terminal for receiving the active column select bit from the output terminal of the first self-decoding page buffer stage, for sensing data from a second bitline, and providing sensed data corresponding to the second bitline on the corresponding data line in response to the active column select bit latched in a subsequent clock signal state.

4. The page buffer of claim 3, wherein a self-decoding operation is executed by

latching the active column select bit in the first self-decoding page buffer stage in response to an opposite clock signal state,

providing the sensed data from the first self-decoding page buffer stage and passing the active column select bit in response to the clock signal state,

latching the active column select bit in the second self-decoding page buffer stage in response to a subsequent opposite clock signal state, and

providing the sensed data from the second self-decoding page buffer stage in response to the subsequent clock signal state.

5. The page buffer of claim 3, wherein the first self-decoding page buffer stage includes

a first segment page buffer for sensing data from the first bitline and providing the sensed data corresponding to the first bitline on the corresponding data line in response to a first enabling signal, and

a first sequential enabler receiving and latching the active column select bit and including the output terminal, the first sequential enabler providing in response to the active column select bit being latched in the clock signal state

the first enabling signal and

the active column select bit from the output terminal.

6. The page buffer of claim 5, wherein the second self-decoding page buffer stage includes

a second segment page buffer for sensing data from the second bitline and providing the sensed data corresponding to the second bitline on the corresponding data line in response to a second enabling signal, and

a second sequential enabler including the input terminal for receiving and latching the active column select bit provided by the first sequential enabler, the second sequential enabler providing in response to the active column select bit being latched in the subsequent clock signal state

the second enabling signal.

7. The page buffer of claim 6, wherein first sequential enabler includes bi-stable circuitry clocked by a clock signal having the clock signal state and a complement of the clock signal state, the bi-stable circuitry including

an input for receiving and latching the active column select bit during the complement of the clock signal state,

the output terminal for providing the active column select during the clock signal state, and

a column select output for providing the first enabling signal having a logic state corresponding to the active column select bit during the clock signal state.

8. The page buffer of claim 6, wherein the first segment page buffer includes a page buffer unit, connected to the first bitline and the corresponding data line.

9. The page buffer of claim 8, wherein the page buffer unit includes

sense circuitry for sensing data of the first bitline, and

a data line coupling circuit for coupling sensed data from the sense circuitry to the corresponding data line in response to the first enabling signal.

10. The page buffer of claim 9, wherein the sense circuitry includes

a precharge circuit for precharging the first bitline.

11. The page buffer of claim 9, wherein the sense circuitry includes

a sensor for sensing the data of the first bitline.

12. The page buffer of claim 11, wherein the data line coupling circuit includes

a column coupling device for coupling the sensor to the corresponding data line in response to the first enabling signal.

13. The page buffer of claim 11, wherein the data line coupling circuit includes

an isolation device for isolating the sensor from the first bitline when the first bitline is being precharged.

14. The page buffer of claim 6, wherein the second segment page buffer includes a page buffer unit, connected to the second bitline and the corresponding data line.

15. The page buffer of claim 14, wherein the page buffer unit includes

sense circuitry for sensing data of the second bitline, and

a data line coupling circuit for providing sensed data from the sense circuitry to the corresponding data line in response to the second enabling signal.

24. The page buffer of claim 8, wherein the first segment page buffer includes first page buffer units each connected to first bitlines and corresponding data line, and

the second segment page buffer includes second page buffer units each connected to second bitlines and the corresponding data lines,

the first bitlines including the first bitline, the second bitlines including the second bitline, and the corresponding data lines including the corresponding data line.

25. The page buffer of claim 24, wherein all the first page buffer units are enabled in response to the first enabling signal and all the second page buffer units are enabled in response to the second enabling signal.