Input/output circuit

• US 8,290,028 B2
• Filed: 05/30/2008
• Issued: 10/16/2012
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Takeuchi, Masahiro
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US12/155,242
• Publication Number:
  US 20080310569A1
• Time in Patent Office: 1,600 Days
• Field of Search: 375/256, 375/257, 375/259, 375/219, 375/295, 375/296, 375/229, 375/230, 375/232, 375/233, 375/355, 375371-376, 375/316, 375/346, 375/350, 329/315, 329/318, 329/347, 329/349, 332/106, 332/107, 332/117, 332/123, 332/149, 332/159, 333/18, 333/28.R
• US Class Current: 375/219
• CPC Class Codes: H03L 7/0993 and a circuit for adding and deleting pulses
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Disclosed is a SERDES circuit including a clock and data recovery circuit that allows operational margin in temporal and voltage directions to be measured, using a phase offset signal and a threshold voltage control signal, a pre-emphasis driver circuit and an equalizer circuit in order to reduce ISI on a transmission line, and an optimization control circuit for controlling the overall circuit. The optimization control circuit controls an equalizer control signal that is for adjusting characteristics of the equalizer circuit and a driver control signal that is for adjusting characteristics of the pre-emphasis driver circuit and sets the equalizer control signal and driver control signal so that the operational margin of the clock and data recovery circuit is maximized.

Claims

1. An input/output circuit comprising:

a clock and data recovery circuit that extracts clock and data from input data, said clock and data recovery circuit capable of measuring an operational margin thereof in a temporal direction and in a voltage direction; and

an optimization control circuit that performs a control so that at least one of a characteristic of a pre-emphasis driver circuit that pre-emphasizes and drives output data and a characteristic of an equalizer circuit that equalizes the input data, are optimized, based on a measurement result of the operational margin of said clock and data recovery circuit.

2. The input/output circuit according to claim 1, comprising:

a transmit circuit including said pre-emphasis driver circuit; and

a receive circuit including;

said equalizer circuit;

said clock and data recovery circuit receiving the input data equalized by said equalizer circuit; and

said optimization control circuit,

wherein said optimization control circuit performs said optimization of the characteristics of said pre-emphasis driver circuit and said equalizer circuit, based on the measurement result of the operational margin of said clock and data recovery circuit.

3. The input/output circuit according to claim 1, comprising:

a transmit circuit including said pre-emphasis driver circuit; and

a receive circuit including said clock and data recovery circuit and said optimization control circuit,

wherein said optimization control circuit performs said optimization of the characteristic of said pre-emphasis driver circuit, based on the measurement result of the operational margin of said clock and data recovery circuit.

4. The input/output circuit according to claim 1, comprising a receive circuit including:

said equalizer circuit;

said clock and data recovery circuit receiving the input data equalized by said equalizer circuit; and

said optimization control circuit,

wherein said optimization control circuit performs said optimization of the characteristic of said equalizer circuit, based on the measurement result of the operational margin of said clock and data recovery circuit.

5. The input/output circuit according to claim 1, comprising:

a parallel-to-serial converting circuit that receives parallel data, converts the parallel data into serial data, and supplies the serial data to said pre-emphasis driver circuit; and

a selection circuit that selects, as the parallel data supplied to said parallel-to-serial converting circuit, either one of parallel data to be transmitted during a normal operation and an opposing driver control signal for controlling a characteristic of a pre-emphasis driver circuit provided in an input/output circuit of an opposing device, said opposing driver control signal being generated by said optimization control circuit.

6. The input/output circuit according to claim 5, comprising:

a serial-to-parallel data converting circuit that converts serial data output from said clock and data recovery circuit into parallel data,

wherein said optimization control circuit monitors the parallel data output from said serial-to-parallel data converting circuit and controls said pre-emphasis circuit of an own device when the opposing driver control signal is received.

7. The input/output circuit according to claim 1, wherein said clock and data recovery circuit comprises:

a data sampling circuit that samples the input data responsive to a clock signal;

a phase comparator that receives the input data sampled by said data sampling circuit and detects a phase relationship between the clock and the sampled input data;

a phase controller that outputs a phase control signal based on a result of a phase comparison by said phase comparator; and

a phase interpolator that generates a clock signal having a phase interpolated based on the phase control signal,

the clock signal from said phase interpolator being supplied to said data sampling circuit, thereby forming a loop,

said phase controller generating another phase control signal different from the phase control signal,

said clock and data recovery circuit further comprising;

another phase interpolator that receives said another phase control signal output from said phase controller and generates another clock signal phase-interpolated based on said another phase control signal;

a threshold voltage generator that generates a threshold voltage;

another data sampling circuit that samples the input data responsive to said another clock signal from said another phase interpolator and the threshold voltage; and

a comparison circuit that compares the data sampled by said data sampling circuit and the data sampled by said another data sampling circuit,

a result of the comparison by said comparison circuit being supplied to said optimization control circuit as an error detection result.

8. The input/output circuit according to claim 7, wherein:

said optimization control circuit supplies to said phase controller a phase offset signal for adding a phase offset between the phase control signal and the other phase control signal generated by said phase controller, thereby variably controlling the phase offset,

said optimization control circuit supplies to said threshold voltage generator a threshold voltage control signal that controls the threshold voltage to be generated by said threshold voltage generator, thereby variably controlling the threshold voltage, and

the measurement of the operational margin of said clock and data recovery circuit in the temporal and voltage directions is carried out by checking whether said another data sampling circuit could correctly sample the data based on the error detection result from said comparison circuit.

9. The input/output circuit according to claim 1, wherein the optimization by said optimization control circuit is executed at power-on.

10. The input/output circuit according to claim 1, wherein the optimization by said optimization control circuit is executed at a first time of the power-on, a result of the optimization is stored in a non-volatile storage device, and the result stored in said storage device is used at subsequent times of the power on.

11. The input/output circuit according to claim 1, wherein:

the optimization by said optimization control circuit is performed at a time of a normal data transmitting operation as well, and

data transmission is performed with the characteristics of at least one of said pre-emphasis driver circuit and said equalizer circuit kept to be optimal with respect to a change in the characteristics of said at least one of said pre-emphasis driver circuit and said equalizer circuit.

12. An interface circuit that converts parallel data, for serial transmission and converts received serially transmitted data into parallel data, including:

the input/output circuit as set forth in claim 1.

13. A semiconductor device including the input/output circuit as set forth in claim 1.

14. A clock and data recovery circuit for a SERDES (SERializer and DESerializer) circuit, said clock and data recovery circuit comprising:

a first data sampling circuit that samples input data;

a phase comparator that receives the input data sampled by said data sampling circuit and detects a phase relationship between a clock signal and the sampled input data;

a phase controller that outputs a phase control signal based on a result of a phase comparison by said phase comparator;

a first phase interpolator that generates a second clock signal having a phase interpolated based on the phase control signal, the clock signal from said phase interpolator being supplied to said data sampling circuit, thereby forming a loop, said phase controller generating a second phase control signal different from the first phase control signal,

a second phase interpolator that receives said second phase control signal output from said phase controller and generates a second clock signal, phase-interpolated based on said second phase control signal;

a threshold voltage generator that generates a threshold voltage;

a second data sampling circuit that samples the input data responsive to said second clock signal from said second phase interpolator and the threshold voltage; and

a comparison circuit that compares the data sampled by said data sampling circuit and the data sampled by said second data sampling circuit, a result of the comparison by said comparison circuit being supplied to an optimization control circuit as an error detection result,

said optimization control circuit performing a control so that at least one of a characteristic of a pre-emphasis driver circuit that pre-emphasizes and drives output data and a characteristic of an equalizer circuit that equalizes the input data, are optimized, as based on the error detection result of said clock and data recovery circuit.

15. The clock and data recovery circuit according to claim 14, wherein:

said optimization control circuit supplies to said phase controller a phase offset signal for adding a phase offset between the first phase control signal and the second phase control signal generated by said phase controller, thereby variably controlling the phase offset,

said optimization control circuit supplies to a threshold voltage generator a threshold voltage control signal that controls a threshold voltage to be generated by said threshold voltage generator, thereby variably controlling the threshold voltage, and

a measurement of an operational margin of said clock and data recovery circuit in a temporal direction and a voltage direction is carried out by checking whether said second data sampling circuit correctly samples the data based on the error detection result from said comparison circuit, given the phase offset due to the phase offset signal and the threshold voltage due to the threshold voltage generator.

16. A method of optimizing a characteristic of at least one of a pre-emphasis driver circuit that pre-emphasizes and drives output data from an input/output circuit and an equalizer circuit that equalizes input data to the input/output circuit, said method comprising:

measuring an operational margin in a temporal direction and in a voltage direction for said input data, using a clock and data recovery circuit that extracts clock and data from the input data; and

by using an optimization control circuit, performing a control so that said at least one characteristic is optimized, based on of the operational margin.

17. The method of claim 16, wherein said input/output circuit comprises a SERDES (SERializer and DESerializer) circuit and said pre-emphasis driver circuit and said equalizer circuit comprise interfaces to a transmission line for said SERDES circuit.

18. The method of claim 16, wherein said measuring of operational margin comprises:

comparing an output from a first data sampling circuit receiving said input data with an output from a second data sampling circuit, the output of the second data sampling circuit being shifted in said temporal direction and said voltage direction; and

determining an amount of shift in said temporal direction and said voltage direction that causes said comparing to no longer match, said amount of shift thereby comprising the operational margin.

19. The method of claim 16, wherein said optimization control circuit optimizes said at least one characteristic by systematically:

changing a setting of said pre-emphasis driver circuit or said equalizer circuit;

determining an effect of the setting change based on an operational margin due to said setting change; and

selecting a setting that provides a marginal operational margin.

20. The method of claim 19, wherein an opposing driver control signal from an opposing input/output circuit is used for optimizing the characteristic of the pre-emphasis driver circuit.