Cache line use history based done bit modification to D-cache replacement scheme

• US 8,291,169 B2
• Filed: 05/28/2009
• Issued: 10/16/2012
• Est. Priority Date: 05/28/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luick, David A.
• Primary Examiner(s): Tran, Denise
• Application Number:
  US12/473,358
• Publication Number:
  US 20100306473A1
• Time in Patent Office: 1,237 Days
• Field of Search: None
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value

Abstract

A method of providing history based done logic includes receiving a cache line in a L2 cache; determining if the cache line has a history of access at least three times on a previous call into the L2 cache; providing the cache line directly to a processor if the history of access was less then the at least three times; and loading the cache line into an L1 cache if the history of access was the at least three times.

Claims

1. A method of providing history based done logic, the method comprising:

receiving a cache line in a L2 cache, the cache line including a history count and a reference count, wherein the reference count is incremented each time the cache line is accessed;

determining if the cache line has a history of access at least three times on a previous call into the L2 cache by comparing the history count to the reference count, and when the history count equals the reference count, incrementing a confirmation count, the confirmation count corresponding to reliability of an estimate that the cache line in the L1 cache is marked as least recently used, and moving an L1 extended cache directory and count flags to an L2 extended cache directory;

providing the cache line directly to a processor if the history of access was less than the at least three times; and

loading the cache line into an L1 cache if the history of access was the at least three times.

2. The method of claim 1, further comprising updating the reference count in the L1 cache and L2 cache each time the cache line is accessed.

3. The method of claim 1, further comprising loading the cache line into a data line buffer for access by the processor if the history of access is equal to two.

4. A processor device, comprising:

a level one (L1) cache;

a level two (L2) cache;

circuitry configured to;

receive a cache line in the L2 cache, the cache line including a history count and a reference count;

determine if the cache line has a history of access at least three times on a previous call into the L2 cache;

provide the cache line directly to a processor if the history of access was less than the at least three times; and

load the cache line into the L1cache if the history of access was the at least three times;

a counter that updates the reference count in the L1 cache each time the cache line is referenced in the L1cache, wherein the counter updates the reference count in the L2 cache each time the cache line is accessed; and

a comparator that compares the history count to the reference count, and a confirmation count that corresponds to reliability of an estimate that the cache line in the L1cache is marked as least recently used, and when the history count equals the reference count, the confirmation count is incremented and an L1extended cache directory and count flags is moved to an L2 extended cache directory.

5. The processor device of claim 4, further comprising a confidence counter that counts each time the reference count is greater than the history count.

6. The processor device of claim 4, further comprising a loader that loads the cache line into a data line buffer for access by the processor if the history of access is equal to two.