Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
First Claim
1. A logic device, comprising:
- first and second data bus interfaces configured to be coupled to a bidirectional data bus,the bidirectional data bus configured to transfer read data in a first direction between the first and second bus interfaces and to transfer write data in a second direction opposite of the first direction between the first and second bus interfaces; and
a bypass circuit coupled to the first and second data bus interfaces and configured to store write data from the bidirectional data bus to transfer the write data from the first data bus interface to the second data bus interface in the second direction instead of over the bidirectional data bus to allow read data to be transferred on the bidirectional data bus from the second data bus interface to the first data bus interface in the first direction, the bypass circuit further configured to restore stored write data to the bidirectional data bus to complete the transfer of the write data,wherein the bypass circuit is configured to be controlled responsive to a bypass signal.
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Accused Products
Abstract
A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
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Citations
17 Claims
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1. A logic device, comprising:
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first and second data bus interfaces configured to be coupled to a bidirectional data bus, the bidirectional data bus configured to transfer read data in a first direction between the first and second bus interfaces and to transfer write data in a second direction opposite of the first direction between the first and second bus interfaces; and a bypass circuit coupled to the first and second data bus interfaces and configured to store write data from the bidirectional data bus to transfer the write data from the first data bus interface to the second data bus interface in the second direction instead of over the bidirectional data bus to allow read data to be transferred on the bidirectional data bus from the second data bus interface to the first data bus interface in the first direction, the bypass circuit further configured to restore stored write data to the bidirectional data bus to complete the transfer of the write data, wherein the bypass circuit is configured to be controlled responsive to a bypass signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory logic circuit comprising:
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first and second data bus interfaces coupled to a bidirectional data bus configured to transfer read data in a first direction between the first and second data bus interfaces and configured transfer write data in a second direction opposite of the first direction between the first and second data bus interfaces; a bypass circuit coupled to the first and second data bus interfaces and configured to store write data from the data bus while read data is transferred over the data bus between the first and second data bus interfaces in the first direction and restore write data to the data bus in the second direction when the read data has finished transmitting; and control logic configured to control the bypass circuit responsive to a bypass signal. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A write data bypass circuit to store and transmit write data on a bidirectional memory bus, comprising:
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a first buffer coupled to the bidirectional bus configured to receive data from and transmit data in a first direction on the bidirectional data bus; a data storage device configured to receive and store write data transmitted in a second direction opposite of the first direction from the bidirectional data bus during the execution of a read operation to prevent a data collision; a multiplexer configured to select between the output of the first buffer or the data storage device; a second buffer coupled to the multiplexer and configured to be enabled or disabled to control output from the write data bypass circuit; and bypass control logic configured to control the multiplexer and the second buffer in order to restore write data to the bidirectional data bus to be transmitted in the second direction thereon, wherein the bypass control logic is configured to be controlled responsive to a bypass signal. - View Dependent Claims (17)
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Specification