Array concatenation in an integrated circuit design

• US 8,291,359 B2
• Filed: 05/07/2010
• Issued: 10/16/2012
• Est. Priority Date: 05/07/2010
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: International Business Machines Corporation
• Inventors: Baumgartner, Jason R., Case, Michael L., Kanzelman, Robert L., Mony, Hari
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US12/775,633
• Publication Number:
  US 20110276932A1
• Time in Patent Office: 893 Days
• Field of Search: 716/103, 716/104, 716/107, 716/111, 716/132
• US Class Current: 716/103
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

Mechanisms are provided in a design environment for array concatenation. The design environment comprises one mechanism to concatenate arrays with enable- and address-compatible ports, thereby reducing the number of arrays in a netlist. The design environment comprises another mechanism to migrate read ports from one array to another based upon compatible enable-, address-, and data-compatible write ports, thereby reducing the number of arrays in a netlist. The design environment comprises yet another mechanism to eliminate unnecessary arrays.

Claims

1. A method, in a data processing system, for minimizing memory array representations, the method comprising:

receiving, in the data processing system, an integrated circuit design having a plurality of memory arrays;

for each memory array in the integrated circuit design, forming a compatibility signature over address and enable pins for all ports;

reducing, by the data processing system, a number of memory arrays in the integrated circuit design to form a reduced integrated circuit design based on the compatibility signatures of the plurality of memory arrays; and

performing, by the data processing system, synthesis or verification on the reduced integrated circuit design.

2. The method of claim 1, wherein reducing the number of memory arrays in the integrated circuit design comprises:

identifying a first memory array and a second memory array, wherein the first memory array and the second memory array are of the same type and are compatible based on their compatibility signatures;

concatenating default initial values and data pins of each port of the second memory array onto compatible ports of the first memory array; and

disconnecting initial value pins and data pins of the second memory array.

3. The method of claim 2, wherein forming the compatibility signature over address and enable pins for a given memory array comprises generating and storing an initialization port compatibility list, a write port compatibility list, and a read port compatibility list;

and

wherein identifying a first memory array and a second memory array comprises determining that the initialization port compatibility list of the first array is compatible with the initialization port compatibility list of the second array and the write port compatibility list of the first array is compatible with the write port compatibility list of the second array and the read port compatibility list of the first array is compatible with the read port compatibility list of the second array.

4. The method of claim 1, wherein reducing the number of memory arrays in the integrated circuit design comprises:

identifying a first memory array and a second memory array, wherein the first memory array and the second memory array are of the same type, default initial values of the first memory array are compatible with default initial values of the second memory array, and the first memory array and the second memory array are compatible based on their compatibility signatures;

migrating all read ports from the second memory array to the first memory array; and

deleting the second memory array.

5. The method of claim 4, wherein forming a compatibility signature over address and enable pins for all ports comprises generating and storing an initialization port obligation list and a write port obligation list;

and

wherein identifying the first memory array and the second memory array comprises determining whether the initialization port obligation list of the first memory array is compatible with the initialization port obligation list of the second memory array and the write port obligation list of the first memory array is compatible with the write port obligation list of the second memory array.

6. The method of claim 1, wherein reducing the number of memory arrays in the integrated circuit design comprises:

identifying a memory array having no read ports or no columns or a number of rows equal to zero; and

deleting the identified memory array.

7. A computer program product comprising a computer readable storage device having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive, in the computing device, an integrated circuit design having a plurality of memory arrays;

for each memory array in the integrated circuit design, form a compatibility signature over address and enable pins for all ports;

reduce, by the computing device, a number of memory arrays in the integrated circuit design to form a reduced integrated circuit design based on the compatibility signatures of the plurality of memory arrays; and

perform, by the computing device, synthesis or verification on the reduced integrated circuit design.

8. The computer program product of claim 7, wherein reducing the number of memory arrays in the integrated circuit design comprises:

identifying a first memory array and a second memory array, wherein the first memory array and the second memory array are of the same type and are compatible based on their compatibility signatures;

concatenating default initial values and data pins of each port of the second memory array onto compatible ports of the first memory array; and

disconnecting initial value pins and data pins of the second memory array.

9. The computer program product of claim 8, wherein forming the compatibility signature over address and enable pins for a given memory array comprises generating and storing an initialization port compatibility list, a write port compatibility list, and a read port compatibility list;

and

wherein identifying a first memory array and a second memory array comprises determining that the initialization port compatibility list of the first array is compatible with the initialization port compatibility list of the second array and the write port compatibility list of the first array is compatible with the write port compatibility list of the second array and the read port compatibility list of the first array is compatible with the read port compatibility list of the second array.

10. The computer program product of claim 7, wherein reducing the number of memory arrays in the integrated circuit design comprises:

identifying a first memory array and a second memory array, wherein the first memory array and the second memory array are of the same type, default initial values of the first memory array are compatible with default initial values of the second memory array, and the first memory array and the second memory array are compatible based on their compatibility signatures;

migrating all read ports from the second memory array to the first memory array; and

deleting the second memory array.

11. The computer program product of claim 10, wherein forming a compatibility signature over address and enable pins for all ports comprises generating and storing an initialization port obligation list and a write port obligation list;

and

wherein identifying the first memory array and the second memory array comprises determining whether the initialization port obligation list of the first memory array is compatible with the initialization port obligation list of the second memory array and the write port obligation list of the first memory array is compatible with the write port obligation list of the second memory array.

12. The computer program product of claim 7, wherein reducing the number of memory arrays in the integrated circuit design comprises:

identifying a memory array having no read ports or no columns or a number of rows equal to zero; and

deleting the identified memory array.

13. The computer program product of claim 7, wherein the computer readable program is stored in a computer readable storage device in a data processing system and wherein the computer readable program was downloaded over a network from a remote data processing system.

14. The computer program product of claim 7, wherein the computer readable program is stored in a computer readable storage device in a server data processing system and wherein the computer readable program is downloaded over a network to a remote data processing system for use in a computer readable storage device with the remote system.

15. An apparatus, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to;

receive an integrated circuit design having a plurality of memory arrays;

for each memory array in the integrated circuit design, form a compatibility signature over address and enable pins for all ports;

reduce a number of memory arrays in the integrated circuit design to form a reduced integrated circuit design based on the compatibility signatures of the plurality of memory arrays; and

perform synthesis or verification on the reduced integrated circuit design.

16. The apparatus of claim 15, wherein reducing the number of memory arrays in the integrated circuit design comprises:

identifying a first memory array and a second memory array, wherein the first memory array and the second memory array are of the same type and are compatible based on their compatibility signatures;

concatenating default initial values and data pins of each port of the second memory array onto compatible ports of the first memory array; and

disconnecting initial value pins and data pins of the second memory array.

17. The apparatus of claim 16, wherein forming the compatibility signature over address and enable pins for a given memory array comprises generating and storing an initialization port compatibility list, a write port compatibility list, and a read port compatibility list;

and

wherein identifying a first memory array and a second memory array comprises determining that the initialization port compatibility list of the first array is compatible with the initialization port compatibility list of the second array and the write port compatibility list of the first array is compatible with the write port compatibility list of the second array and the read port compatibility list of the first array is compatible with the read port compatibility list of the second array.

18. The apparatus of claim 15, wherein reducing the number of memory arrays in the integrated circuit design comprises:

identifying a first memory array and a second memory array, wherein the first memory array and the second memory array are of the same type, default initial values of the first memory array are compatible with default initial values of the second memory array, and the first memory array and the second memory array are compatible based on their compatibility signatures;

migrating all read ports from the second memory array to the first memory array; and

deleting the second memory array.

19. The apparatus of claim 18, wherein forming a compatibility signature over address and enable pins for all ports comprises generating and storing an initialization port obligation list and a write port obligation list;

and

wherein identifying the first memory array and the second memory array comprises determining whether the initialization port obligation list of the first memory array is compatible with the initialization port obligation list of the second memory array and the write port obligation list of the first memory array is compatible with the write port obligation list of the second memory array.

20. The apparatus of claim 15, wherein reducing the number of memory arrays in the integrated circuit design comprises:

identifying a memory array having no read ports or no columns or a number of rows equal to zero; and

deleting the identified memory array.