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Array concatenation in an integrated circuit design

  • US 8,291,359 B2
  • Filed: 05/07/2010
  • Issued: 10/16/2012
  • Est. Priority Date: 05/07/2010
  • Status: Active Grant
First Claim
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1. A method, in a data processing system, for minimizing memory array representations, the method comprising:

  • receiving, in the data processing system, an integrated circuit design having a plurality of memory arrays;

    for each memory array in the integrated circuit design, forming a compatibility signature over address and enable pins for all ports;

    reducing, by the data processing system, a number of memory arrays in the integrated circuit design to form a reduced integrated circuit design based on the compatibility signatures of the plurality of memory arrays; and

    performing, by the data processing system, synthesis or verification on the reduced integrated circuit design.

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