Automated digital circuit design tool that reduces or eliminates adverse timing constraints do to an inherent clock signal skew, and applications thereof

• US 8,291,364 B2
• Filed: 02/15/2011
• Issued: 10/16/2012
• Est. Priority Date: 10/26/2007
• Status: Active Grant

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Panigrahi, Avishek, Banerjee, Soumya, Chanak, Thomas Stephen Jr.
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US13/027,917
• Publication Number:
  US 20110138349A1
• Time in Patent Office: 609 Days
• Field of Search: 716/108, 716/113, 716/122, 716/134, 326/41, 326/47, 326/101, 326/93
• US Class Current: 716/122
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.

Claims

1. A digital circuit, comprising:

a clocking system configured to reduce clock skew;

a clock gater associated with the clocking system;

a clock pin associated with a register, wherein the clock pin selectively drives an enable pin of the clock gater; and

a buffered clock tree configured to provide a selectable early clock signal to the clock pin, of the register,

wherein the clock gater is identified as a top level clock gater when a number of registers driven by the clock gater, compared to a summing of a total number of registers, exceeds a threshold value.

2. The digital circuit of claim 1, wherein the buffered clock tree is configured to select a number of clock buffers between a clock signal generator and the register.

3. The digital circuit of claim 1, wherein the buffered clock tree is configured to select a size of a clock buffer between a clock signal generator and the register.

4. The digital circuit of claim 1, wherein the buffered clock tree is configured to determine an insertion delay associated with a clock signal output by the clock gater, and provide an early clock signal to the register based on the determined insertion delay.

5. The digital circuit of claim 4, wherein the buffered clock tree is further configured to determine a maximum insertion delay associated with a clock signal output by the clock gater.

6. The digital circuit of claim 4, wherein the buffered clock tree is further configured to determine an average insertion delay associated with a clock signal output by the clock gater.

7. The digital circuit of claim 1, wherein the buffered clock tree is configured to provide:

a first early clock signal to a first plurality of registers belonging to a first clock gater driving register stage; and

a second early clock signal to a second plurality of registers belonging to a second clock gater driving register stage.