Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL)

• US 8,293,605 B2
• Filed: 02/25/2011
• Issued: 10/23/2012
• Est. Priority Date: 02/25/2011
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Baars, Peter, Lepper, Marco, Fitz, Clemens
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/034,902
• Publication Number:
  US 20120220086A1
• Time in Patent Office: 606 Days
• Field of Search: 257/E21.4, 257/E21.471, 257/E21.483, 257/E21.497
• US Class Current: 438/275
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.

Claims

1. A method for fabricating a CMOS integrated circuit comprising:

epitaxially growing embedded silicon germanium in regions of a semiconductor substrate;

forming SiGe-stressed source and drain regions in the embedded silicon germanium;

forming non-SiGe-stressed source and drain regions in the semiconductor substrate;

forming nickel silicide contacts in the SiGe-stressed source and drain regions and in the non-SiGe-stressed source and drain regions;

depositing a tensile insulating layer overlying the nickel silicide contacts by a first process of plasma enhanced deposition prior to depositing a compressive insulating layer;

removing a portion of the tensile insulating layer overlying the SiGe-stressed source and drain regions, leaving a remaining portion of the tensile insulating layer overlying all of the non-SiGe-stressed source and drain regions and thereafter curing the remaining portion;

depositing the compressive insulating layer overlying the SiGe-stressed source and drain regions and the remaining portion of the tensile insulating layer by a second process of plasma enhanced deposition after curing the remaining portion of the tensile insulating layer; and

removing a portion of the compressive insulating layer overlying the remaining portion of the tensile insulating layer.

2. The method of claim 1 further comprising:

forming first gate electrode structures and second gate electrode structures on the semiconductor substrate.

3. The method of claim 2, wherein epitaxially growing the embedded silicon germanium comprises:

epitaxially growing the embedded silicon germanium around and in alignment with the first gate electrode structures.

4. The method of claim 2 further comprising:

implanting conductivity determining ions into the embedded silicon germanium to form the SiGe-stressed source and drain regions in alignment with the first gate electrode structures and implanting conductivity determining ions into the semiconductor substrate to form the non-SiGe-stressed source and drain regions in alignment with the second gate electrode structures.

5. The method of claim 1 wherein curing the remaining portion comprises exposing the remaining portion to ultraviolet radiation.

6. The method of claim 5 wherein exposing the remaining portion to ultraviolet radiation comprises exposing the remaining portion to ultraviolet radiation to raise the remaining portion to a temperature of about 400°

C.

7. The method of claim 6 wherein depositing a tensile insulating layer comprises depositing a silicon nitride layer by a process of plasma enhanced deposition at a temperature of about 400°

C.

8. A method for fabricating a CMOS integrated circuit comprising:

forming first gate structures and second gate structures on a semiconductor substrate;

epitaxially growing embedded SiGe in portions of the semiconductor substrate around and in alignment with the first gate structures;

forming SiGe-stressed source and drain regions in the embedded SiGe around the first gate structures and non-stressed source and drain regions around the second gate structures;

forming nickel silicide contacts in the SiGe-stressed source and drain regions and in the non-stressed source and drain regions;

depositing a tensile nitride layer overlying the nickel silicide contacts in the SiGe-stressed source and drain regions and in the non-stressed source and drain regions by a first process of plasma enhanced chemical vapor deposition prior to depositing a compressive nitride layer;

removing a portion of the tensile nitride layer overlying the SiGe-stressed source and drain regions and thereafter curing the tensile nitride layer overlying all of the nickel silicide contacts in the non-stressed source and drain regions with ultraviolet radiation; and

depositing the compressive nitride layer overlying the SiGe-stressed source and drain regions by a second process of plasma enhanced chemical vapor deposition after curing the tensile nitride layer.

9. The method of claim 8 wherein curing the tensile nitride layer comprises curing the nitride layer at a temperature of about 400°

C.

10. The method of claim 9 wherein depositing a tensile nitride layer comprises depositing the tensile nitride layer at a temperature of about 400°

C.

11. The method of claim 8 further comprising removing a portion of the compressive nitride layer overlying the non-stressed source and drain regions.

12. A method for fabricating a CMOS integrated circuit comprising:

depositing a tensile stress layer overlying a semiconductor substrate including SiGe-stressed source and drain regions and non-stressed source and drain regions by a first process of plasma enhanced deposition prior to depositing a compressive stress layer overlying the semiconductor substrate, wherein nickel silicide contacts are formed overlying the SiGe-stressed source and drain regions and the non-stressed source and drain regions;

removing the tensile stress layer overlying the SiGe-stressed source and drain regions and leaving a remaining portion of the tensile stress layer covering the non-stressed source and drain regions before applying a curing radiation;

applying a curing radiation to the remaining portion; and

depositing the compressive stress layer overlying the semiconductor substrate and the remaining portion by a second process of plasma enhanced deposition after applying the curing radiation.

13. The method of claim 12 wherein applying a curing radiation comprises ultraviolet irradiating the remaining portion to a temperature of about 400°

C.

14. The method of claim 13 wherein depositing a tensile stress layer comprises depositing a tensile nitride layer at a temperature of about 400°

C.