Integrated circuit devices including low-resistivity conductive patterns in recessed regions
First Claim
1. An integrated circuit device, comprising:
- a substrate;
a device isolation pattern on the substrate defining an active area therein, the active area including a doped region therein;
a conductive pattern extending on the active area and electrically contacting the doped region, the conductive pattern having a lower resistivity than the doped region, wherein the conductive pattern is disposed in a recessed region having a bottom surface that is lower than a top surface of the active area;
a channel pillar electrically contacting the doped region and extending therefrom in a direction away from the substrate;
a conductive gate electrode on a sidewall of the channel pillar; and
a gate dielectric layer between the gate electrode and the sidewall of the channel pillar.
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Accused Products
Abstract
An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar.
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Citations
18 Claims
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1. An integrated circuit device, comprising:
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a substrate; a device isolation pattern on the substrate defining an active area therein, the active area including a doped region therein; a conductive pattern extending on the active area and electrically contacting the doped region, the conductive pattern having a lower resistivity than the doped region, wherein the conductive pattern is disposed in a recessed region having a bottom surface that is lower than a top surface of the active area; a channel pillar electrically contacting the doped region and extending therefrom in a direction away from the substrate; a conductive gate electrode on a sidewall of the channel pillar; and a gate dielectric layer between the gate electrode and the sidewall of the channel pillar. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14)
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12. An integrated circuit device, comprising:
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a substrate; a device isolation pattern on the substrate defining an active area therein, the active area including a doped region therein; a conductive pattern extending on the active area and electrically contacting the doped region, the conductive pattern having a lower resistivity than the doped region; a channel pillar electrically contacting the doped region and extending therefrom in a direction away from the substrate; a conductive gate electrode on a sidewall of the channel pillar; a gate dielectric layer between the gate electrode and the sidewall of the channel pillar; and a hard mask pattern on a top surface of the active area, wherein the channel pillar contacts the top surface of the active area and extends through the hard mask pattern, and wherein a top surface of the hard mask pattern is substantially coplanar with a top surface of the conductive pattern and with a top surface of the device isolation pattern.
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15. An integrated circuit device, comprising:
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a substrate; a device isolation pattern on the substrate defining an active area therein, the active area including a doped region therein; a conductive pattern extending on the active area and electrically contacting the doped region, the conductive pattern having a lower resistivity than the doped region; a channel pillar electrically contacting the doped region and extending therefrom in a direction away from the substrate; a conductive gate electrode on a sidewall of the channel pillar; a gate dielectric layer between the gate electrode and the sidewall of the channel pillar; and a data storage element electrically connected to a top surface of the channel pillar. - View Dependent Claims (16, 17, 18)
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Specification