Integrated circuit devices including low-resistivity conductive patterns in recessed regions

• US 8,294,131 B2
• Filed: 06/30/2010
• Issued: 10/23/2012
• Est. Priority Date: 07/23/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Kang-Uk, Oh, Yongchul, Kim, Hui-Jung, Chung, Hyun-Woo, Kim, Hyun-Gi
• Primary Examiner(s): Smith, Bradley K
• Assistant Examiner(s): Valentine, Jami M
• Application Number:
  US12/826,896
• Publication Number:
  US 20110017971A1
• Time in Patent Office: 846 Days
• Field of Search: 257 2- 5, 257/E29.002, 438102-103
• US Class Current: 257/2
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays

Abstract

An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar.

Claims

1. An integrated circuit device, comprising:

a substrate;

a device isolation pattern on the substrate defining an active area therein, the active area including a doped region therein;

a conductive pattern extending on the active area and electrically contacting the doped region, the conductive pattern having a lower resistivity than the doped region, wherein the conductive pattern is disposed in a recessed region having a bottom surface that is lower than a top surface of the active area;

a channel pillar electrically contacting the doped region and extending therefrom in a direction away from the substrate;

a conductive gate electrode on a sidewall of the channel pillar; and

a gate dielectric layer between the gate electrode and the sidewall of the channel pillar.

2. The device of claim 1, wherein the doped region, the recessed region, and the conductive pattern extend in a first direction, and wherein the gate electrode extends in a second direction substantially perpendicular to the first direction.

3. The device of claim 1, wherein the conductive pattern comprises an upper surface and a lower surface, wherein the lower surface of the conductive pattern is below a top surface of the device isolation pattern and the top surface of the active area, and wherein the bottom surface of the recessed region comprises a recessed surface of the device isolation pattern.

4. The device of claim 3, wherein the active area comprises a recessed surface lower than the top surface of the active area, and wherein the bottom surface of the recessed region includes the recessed surface of the device isolation pattern and the recessed surface of the active area.

5. The device of claim 4, wherein the recessed region comprises a first sidewall extending between the top and recessed surfaces of the device isolation pattern, and a second sidewall extending between the top and recessed surfaces of the active area, and further comprising:

first and second sidewall spacers electrically separating the conductive pattern from the first and second sidewalls of the recessed region, respectively, such that the conductive pattern contacts the recessed surface of the active area and the recessed surface of the device isolation pattern.

6. The device of claim 1, wherein the active area includes a recessed surface lower than the top surface of the active area, and wherein the bottom surface of the recessed region comprises the recessed surface of the active area.

7. The device of claim 1, wherein the recessed region and the conductive pattern extend in a first direction, wherein the gate electrode extends in a second direction substantially perpendicular to the first direction, and wherein the doped region and the active area extend in a third direction that is not perpendicular to the first direction and is not parallel to the first direction.

8. The device of claim 7, wherein the device isolation pattern includes a top surface and a recessed surface, wherein the recessed surface of the device isolation pattern is lower than the top surface of the device isolation pattern and the top surface of the active area, and wherein the bottom surface of the recessed region comprises the recessed surface of the device isolation pattern.

9. The device of claim 8, wherein the conductive pattern is in contact with a sidewall of the active area, and wherein an entirety of the top surface of the active area comprises a substantially planar surface.

10. The device of claim 8, wherein the recessed region and the conductive pattern extend in the first direction across the active area, wherein the active area includes a recessed surface lower than the top surface thereof, and wherein the bottom surface of the recessed region further comprises the recessed surface of the active area.

11. The device of claim 1, further comprising:

an insulating layer electrically isolating the gate electrode and the active area, and electrically isolating the gate electrode and the conductive pattern.

13. The device of claim 1, wherein the gate electrode comprises a first portion and a second portion adjacent thereto extending in a first direction, wherein the first portion surrounds the channel pillar and has a first width along a second direction substantially perpendicular to the first direction, and wherein the second portion has a second width narrower than the first width along the second direction.

14. The device of claim 1, wherein the doped region has a lower boundary opposite the top surface of the active area, and wherein the lower boundary of the doped region is below the bottom surface of the recessed region.

12. An integrated circuit device, comprising:

a substrate;

a device isolation pattern on the substrate defining an active area therein, the active area including a doped region therein;

a conductive pattern extending on the active area and electrically contacting the doped region, the conductive pattern having a lower resistivity than the doped region;

a channel pillar electrically contacting the doped region and extending therefrom in a direction away from the substrate;

a conductive gate electrode on a sidewall of the channel pillar;

a gate dielectric layer between the gate electrode and the sidewall of the channel pillar; and

a hard mask pattern on a top surface of the active area,

wherein the channel pillar contacts the top surface of the active area and extends through the hard mask pattern, and wherein a top surface of the hard mask pattern is substantially coplanar with a top surface of the conductive pattern and with a top surface of the device isolation pattern.

15. An integrated circuit device, comprising:

a substrate;

a device isolation pattern on the substrate defining an active area therein, the active area including a doped region therein;

a conductive pattern extending on the active area and electrically contacting the doped region, the conductive pattern having a lower resistivity than the doped region;

a channel pillar electrically contacting the doped region and extending therefrom in a direction away from the substrate;

a conductive gate electrode on a sidewall of the channel pillar;

a gate dielectric layer between the gate electrode and the sidewall of the channel pillar; and

a data storage element electrically connected to a top surface of the channel pillar.

16. The device of claim 15, wherein the data storage element comprises one of a capacitor and a variable resistivity memory element.

17. The device of claim 15, wherein the data storage element comprises a resistive random access memory (RRAM) element, a phase changeable random access memory (PRAM) element, and/or a magnetic random access memory (MRAM) element.

18. The device of claim 15, wherein the data storage element comprises a string of serially connected memory cells.