4 F 2 memory cell array
First Claim
1. An integrated circuit including a memory cell array comprising:
- active area lines;
bitlines arranged such that individual bitlines intersect a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch;
wordlines arranged such that individual wordlines intersect a plurality of the active area lines, and individual wordlines intersect a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein;
neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines;
the bitline pitch is different from the wordline pitch; and
the size of a memory cell corresponds to 4 F2.
3 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and the bitline pitch is different from the wordline pitch.
21 Citations
46 Claims
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1. An integrated circuit including a memory cell array comprising:
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active area lines; bitlines arranged such that individual bitlines intersect a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch; wordlines arranged such that individual wordlines intersect a plurality of the active area lines, and individual wordlines intersect a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein; neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines; the bitline pitch is different from the wordline pitch; and the size of a memory cell corresponds to 4 F2. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An integrated circuit including a memory cell array comprising:
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bitlines generally extending along a first direction, the bitlines being arranged at a bitline pitch; wordlines running along a second direction, the wordlines being arranged at a wordline pitch; active areas, transistors being formed in the active areas, the active areas extending in a direction that is slanted with respect to the first and second directions, bitline contacts disposed in regions generally defined by an intersection of a bitline and a corresponding active area; wherein; neighboring bitline contacts that are shifted along a direction that is slanted with respect to the first and second directions, respectively, are connected with neighboring bitlines; the bitline pitch is different from the wordline pitch; and the size of a memory cell corresponds to 4 F2. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. An integrated circuit including a memory cell array comprising:
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bitlines generally extending along a first direction, the bitlines being arranged at a bitline pitch; wordlines running along a second direction, the wordlines being arranged at a wordline pitch, the wordlines being disposed so that a bottom side of the wordlines is disposed below a substrate surface; the bitlines and the wordlines being connected with corresponding memory cells; wherein the bitline pitch is different from the wordline pitch, and the size of a memory cell corresponds to 4 F2. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. An integrated circuit including a memory cell array comprising:
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active area lines; bitlines arranged such that individual bitlines intersect a plurality of the active area lines to form bitline contacts, respectively, the bitlines being arranged at a bitline pitch; wordlines arranged such that individual wordlines intersect a plurality of the active area lines, and individual wordlines intersect a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein; neighboring bitline contacts, each of which is connected to one of the active area lines, are connected with different bitlines; the bitline pitch is different from the wordline pitch; and the wordline pitch is 4/3F. - View Dependent Claims (43)
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44. An integrated circuit including a memory cell array comprising:
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bitlines generally extending along a first direction, the bitlines being arranged at a bitline pitch; wordlines running along a second direction, the wordlines being arranged at a wordline pitch; active areas, transistors being formed in the active areas, the active areas extending in a direction that is slanted with respect to the first and second directions, bitline contacts disposed in regions generally defined by an intersection of a bitline and a corresponding active area; wherein; neighboring bitline contacts that are shifted along a direction that is slanted with respect to the first and second directions, respectively, are connected with neighboring bitlines; the bitline pitch is different from the wordline pitch; and the wordline pitch is 4/3F. - View Dependent Claims (45)
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46. An integrated circuit including a memory cell array comprising:
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bitlines generally extending along a first direction, the bitlines being arranged at a bitline pitch; wordlines running along a second direction, the wordlines being arranged at a wordline pitch, the wordlines being disposed so that a bottom side of the wordlines is disposed below a substrate surface; the bitlines and the wordlines being connected with corresponding memory cells; wherein the bitline pitch is different from the wordline pitch, and the wordline pitch is 4/3F.
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Specification