Methods and apparatus for SRAM bit cell with low standby current, low supply voltage and high speed

• US 8,294,212 B2
• Filed: 03/26/2010
• Issued: 10/23/2012
• Est. Priority Date: 09/18/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Ping-Wei, Yang, Chang-Ta, Mii, Yuh-Jier
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): NEWTON, VALERIE N
• Application Number:
  US12/748,098
• Publication Number:
  US 20110068400A1
• Time in Patent Office: 942 Days
• Field of Search: None
• US Class Current: 257/347
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

Circuits and methods for providing an SRAM or CAM bit cell. In one embodiment, a bit cell portion with thicker gate oxides in the storage cell transistors, and thinner gate oxides in a read port section having transistors are disclosed. The use of the thick gate oxides in the storage cell transistors provides a stable storage of data and lower standby leakage current. The use of the thinner gate oxides in the read port transistors provides fast read accesses and allows a lower Vcc,min in the read port. The methods used to form the dual gate oxide thickness SRAM cells have process steps compatible with the existing semiconductor manufacturing processes. Embodiments using high k gate dielectrics, dual gate dielectric materials in a single bit cell, and using finFET and planar devices in a bit cell are described. Methods for forming the structures are disclosed.

Claims

1. An apparatus, comprising:

a semiconductor substrate; and

at least one SRAM bit cell formed in a portion of the semiconductor substrate;

wherein the at least one SRAM bit cell further comprises a first 6T storage cell comprising NMOS transistors having a first gate dielectric thickness and a read port comprising NMOS transistors having a second thinner gate dielectric thickness;

wherein the second thinner gate dielectric thickness is greater than 75% and less than 99% of the first gate dielectric thickness.

2. The apparatus of claim 1, wherein the second thinner gate dielectric thickness is greater than 85% and less than 95% of the first gate dielectric thickness.

3. The apparatus of claim 1, wherein the second thinner gate dielectric thickness is greater than 85% and less than 90% of the first gate dielectric thickness.

4. The apparatus of claim 1, wherein the SRAM bit cell is one selected from the group of an 8T SRAM bit cell and a 10T SRAM cell.

5. The apparatus of claim 1, wherein the SRAM bit cell comprises at least one finFET transistor.

6. The apparatus of claim 1, further comprising:

first and second metal layers disposed over the substrate and being separated by intervening interlevel dielectric layers, coupling at least some of the transistors of the SRAM bit cell together; and

a read bit line formed in the first metal layer that overlies the substrate with no intervening metal layers, coupled to the read port of the SRAM bit cell using a contact and without any intervening metal layer to metal layer vias.

7. The apparatus of claim 1, wherein:

the SRAM bit cell is one selected from the group of an 8T SRAM bit cell and a 10T SRAM cell; and

the read port comprises at least one finFET transistor.

8. The apparatus of claim 1, wherein the first and second gate dielectrics further comprise silicon oxide.

9. The apparatus of claim 1, wherein at least one of the first thicker gate dielectric and second thinner gate dielectric comprise a high k dielectric.

10. The apparatus of claim 1, wherein the first thicker gate dielectric and second thinner gate dielectric comprise a dielectric selected from the group of silicon oxide, silicon dioxide, silicon nitride, and silicon oxynitride.

11. An integrated circuit, comprising:

a logic portion formed in a first portion of a semiconductor substrate and having transistors, including some transistors having gate dielectrics of a thin gate dielectric; and

an SRAM array comprising;

a plurality of SRAM bit cells, each comprising;

an SRAM bit cell formed in a second portion of the semiconductor substrate; and

the SRAM bit cell further comprising transistors having a thicker gate dielectric and additional transistors coupled to the thicker gate dielectric transistors and having the thin gate dielectric;

wherein the thin gate dielectric has a thickness that is less than 95% of the thickness of the thicker gate dielectric.

12. The integrated circuit of claim 11, wherein the thin gate dielectric thickness is between 75% and 99% of the thicker gate dielectric thickness.

13. The integrated circuit of claim 11, wherein the SRAM bit cell comprises a first 6T storage cell of NMOS transistors having the thicker gate dielectric;

and further comprising a read port of NMOS transistors having the thin gate dielectric.

14. The integrated circuit of claim 13, wherein the SRAM bit cells each further comprise:

first and second metal layers disposed over the SRAM array and being separated from the SRAM array and from one another by intervening interlevel dielectric layers, and coupling at least some of the transistors of the SRAM bit cells together; and

a read bit line formed in the first metal layer that overlies the SRAM array with no intervening metal layers, coupled to the read portion of the SRAM bit cells without any intervening metal layer to metal layer vias.

15. An apparatus, comprising:

a semiconductor substrate;

at least one content addressable memory (CAM) bit cell formed in a portion of the semiconductor substrate;

a logic portion formed in a first portion of the semiconductor substrate apart from the portion of the semiconductor substrate comprising the CAM bit cell and having transistors, the transistors including some having gate dielectrics of a thin gate dielectric;

wherein the CAM bit cell further comprises transistors having a first gate dielectric of a first thickness and additional transistors having a second thinner gate dielectric that is equal to the thin gate dielectric; and

wherein the second thinner gate dielectric has a thickness greater than 75% and less than 99% of the first gate dielectric thickness.

16. The apparatus of claim 15, wherein the portion of the semiconductor substrate comprising the at least one CAM bit cell further comprises a silicon on insulator (SOI) layer.

17. The apparatus of claim 15, wherein the CAM bit cell further comprises at least one finFET transistor.

18. The apparatus of claim 15, wherein the second thinner gate dielectric has a thickness greater than 85% and less than 95% of the first gate dielectric thickness.