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Methods and apparatus for SRAM bit cell with low standby current, low supply voltage and high speed

  • US 8,294,212 B2
  • Filed: 03/26/2010
  • Issued: 10/23/2012
  • Est. Priority Date: 09/18/2009
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a semiconductor substrate; and

    at least one SRAM bit cell formed in a portion of the semiconductor substrate;

    wherein the at least one SRAM bit cell further comprises a first 6T storage cell comprising NMOS transistors having a first gate dielectric thickness and a read port comprising NMOS transistors having a second thinner gate dielectric thickness;

    wherein the second thinner gate dielectric thickness is greater than 75% and less than 99% of the first gate dielectric thickness.

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