Chip package with dam bar restricting flow of underfill

• US 8,294,279 B2
• Filed: 01/24/2006
• Issued: 10/23/2012
• Est. Priority Date: 01/25/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Chen, Ke-Hung, Lin, Shih-Hsiung, Lin, Mou-Shiung
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): Tran, Thanh Y
• Application Number:
  US11/307,127
• Publication Number:
  US 20060220259A1
• Time in Patent Office: 2,464 Days
• Field of Search: 257/737, 257/738, 257/777, 257778-784, 257/686, 257/723, 257/688, 257/690, 257/734, 257787-795, 257/758, 257/730, 257/750, 257/751, 257/691, 257/678, 257/774, 438/108, 438/109, 438/127, 438/118, 438/612, 438/613, 438/614
• US Class Current: 257/777
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13109 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13118 : Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/1312 : Antimony [Sb] as principal constituent
• CPC Class Codes: H01L 2224/13123 : Magnesium [Mg] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/26145 : Flow barriers
• CPC Class Codes: H01L 2224/26175 : Flow barriers
• CPC Class Codes: H01L 2224/27013 : for holding or confining the layer connector, e.g. solder flow barrier
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/29109 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83051 : Forming additional members, e.g. dam structures
• CPC Class Codes: H01L 2224/83365 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/0134 : Quaternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

Claims

1. A chip package comprising:

a circuit component having a top surface with a first region and a second region, wherein said circuit component comprises multiple first metal pads at said second region, wherein said multiple first metal pads are arranged substantially in a direction from a top perspective view, and wherein a ditch in said circuit component extends substantially in said direction from said top perspective view;

a chip vertically over said first region, wherein said second region has no area vertically under said chip;

multiple metal bumps between said chip and said first region, wherein one of said multiple metal bumps has a top end joining said chip and a bottom end joining said first region, wherein said multiple metal bumps connect said chip to said circuit component;

an underfill between said chip and said first region and between said multiple metal bumps; and

a dam bar on and in contact with said second region, wherein said dam bar comprises a metal, wherein from said top perspective view, said dam bar extends substantially in said direction and is located between an outer edge of said chip and an outer edge of said multiple first metal pads, wherein said dam bar contacts said underfill, and wherein said ditch is between said dam bar and said multiple metal bumps and there is no metal bump located between said ditch and said multiple first metal pads.

2. The chip package of claim 1, wherein said dam bar has a thickness between 20 and 300 micrometers.

3. The chip package of claim 1, wherein said dam bar has a thickness between 30 and 100 micrometers.

4. The chip package of claim 1, wherein said chip has an edge vertically over said ditch, wherein said ditch is over a region of a metal piece of said circuit component, and said region of said metal piece is at a bottom of said ditch, and wherein said underfill is further in said ditch and on said region of said metal piece.

5. The chip package of claim 1, wherein said edge of said chip extends substantially in said direction from said top perspective view.

6. The chip package of claim 1, wherein said dam bar surrounds said first region.

7. The chip package of claim 1, wherein said multiple first metal pads are configured to be wirebonded thereto.

8. The chip package of claim 1, wherein said circuit component comprises another chip.

9. The chip package of claim 1, wherein said circuit component further comprises:

a semiconductor substrate;

multiple MOS devices on said semiconductor substrate;

a metallization structure over said semiconductor substrate;

multiple second metal pads over said semiconductor substrate; and

a passivation layer over said metallization structure and over said semiconductor substrate, wherein multiple openings in said passivation layer are over multiple contact points of said multiple second metal pads, and said multiple contact points are at multiple bottoms of said multiple openings, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers, wherein said multiple metal bumps are connected to said multiple contact points through said multiple openings.

10. The chip package of claim 9, wherein said circuit component further comprises multiple metal traces over said passivation layer and on said multiple contact points, wherein said multiple metal traces connect said multiple metal bumps to said multiple contact points through said multiple openings, wherein said multiple metal traces comprise a gold layer having a thickness greater than 1 micrometer.

11. The chip package of claim 10, wherein said multiple metal traces further comprise a titanium-containing layer under said gold layer.

12. The chip package of claim 1, wherein said multiple metal bumps comprise a tin-containing layer between said chip and said first region.

13. The chip package of claim 12, wherein said multiple metal bumps further comprise a nickel-containing layer between said tin-containing layer and said first region, and a copper layer between said nickel-containing layer and said first region.

14. A chip package comprising:

a circuit component having a top surface with a first region and a second region, wherein said circuit component comprises multiple first metal pads at said second region, wherein said multiple first metal pads are arranged in a direction from a top perspective view, wherein a ditch in said circuit component extends substantially in said direction from said top perspective view, wherein said ditch is over a region of a metal piece of said circuit component, and said region of said metal piece is at a bottom of said ditch;

a chip vertically over said first region, wherein said second region has no area vertically under said chip;

multiple metal bumps between said chip and said first region, wherein one of said multiple metal bumps has a top end joining said chip and a bottom end joining said first region, wherein said multiple metal bumps connect said chip to said circuit component, wherein from said top perspective view, said ditch is between said multiple first metal pads and said multiple metal bumps wherein no metal bump is between said ditch and said multiple first metal pads; and

an underfill between said chip and said first region, between said multiple metal bumps in said ditch and on said region, wherein no metal bump is over said region.

15. The chip package of claim 14, wherein said circuit component further comprises:

a semiconductor substrate;

multiple MOS devices on said semiconductor substrate;

a metallization structure over said semiconductor substrate;

multiple second metal pads over said semiconductor substrate; and

a passivation layer over said metallization structure and over said semiconductor substrate, wherein multiple openings in said passivation layer are over multiple contact points of said multiple second metal pads, and said multiple contact points are at multiple bottoms of said multiple openings, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers, wherein said multiple metal bumps are connected to said multiple contact points through said multiple openings.

16. The chip package of claim 14, wherein said ditch is in a polymer layer of said circuit component.

17. The chip package of claim 14, wherein said multiple first metal pads are configured to be wirebonded thereto.

18. The chip package of claim 14, wherein said circuit component comprises another chip.

19. The chip package of claim 14, wherein said multiple metal bumps comprise a tin-containing layer between said chip and said first region.