Testing of multiple integrated circuits

• US 8,294,483 B2
• Filed: 05/30/2008
• Issued: 10/23/2012
• Est. Priority Date: 05/30/2008
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (FIG LLC (d/b/a Fortress Investment Group LLC))
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Pessoa, Lucio F. C., Pelley, Perry H. III
• Primary Examiner(s): Koval, Melissa
• Assistant Examiner(s): Chan, Emily Y
• Application Number:
  US12/130,173
• Publication Number:
  US 20090295415A1
• Time in Patent Office: 1,607 Days
• Field of Search: 324750-765, 714/733, 714/758, 702/182
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT

Abstract

A testing system includes a tester probe and a plurality of integrated circuits. Tests are broadcast to the plurality of integrated circuits using carrierless ultra wideband (UWB) radio frequency (RF). All of the plurality of integrated circuits receive, at the same time, test input signals by way of carrierless UWB RF and all of the plurality of integrated circuits run tests and provide results based on the test input signals. Thus, the plurality of integrated circuits are tested simultaneously which significantly reduces test time. Also the tests are not inhibited by physical contact with the integrated circuits.

Claims

1. A method for testing one or more integrated circuits, comprising:

simultaneously receiving via carrierless UWB radio frequency signaling an input test value from one antenna of a test probe at a first input of a first integrated circuit and at a second input of a second integrated circuit;

providing, from a first output of the first integrated circuit, a first output test value generated in response to the input test value by transmitting, via wired signaling, the first output test value from the first integrated circuit to a tester station, the test probe coupled to the tester station; and

providing, from a second output of the second integrated circuit, a second output test value generated in response to the input test value,

wherein the first output of the first integrated circuit and the second output of the second integrated circuit are configured as a scan chain to output the first output test value and the second output test value.

2. A method for testing a plurality of die in a wafer comprising:

providing a semiconductor wafer having a first die and a second die;

simultaneously receiving via carrierless UWB radio frequency signaling an input test value from one antenna of a test probe at a first input of the first die and at a second input of the second die;

providing, from a first output of the first die, a first output test value generated in response to the input test value;

providing, from a second output of the second die, a second output test value generated in response to the input test value;

after the providing the first output test value and the providing the second output test value, singulating the wafer; and

transmitting, via a wire, the first output test value from the first die to a tester station, the test probe coupled to the tester station.

3. The method of claim 2, wherein the first output of the first die and the second output of the second die are configured as a scan chain to output the first output test value and the second output test value.