Multiple RF-port modulator for RFID tag

• US 8,294,582 B1
• Filed: 09/25/2009
• Issued: 10/23/2012
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Humes, Todd E., Oliver, Ronald A.
• Primary Examiner(s): Lieu, Julie
• Application Number:
  US12/567,520
• Time in Patent Office: 1,124 Days
• Field of Search: None
• US Class Current: 340/572.7
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

Apparatus and systems may include integrated circuits for use with Radio Frequency Identification (RFID) tags having an antenna structure with at least three coupling ends. The integrated circuits may include three or more nodes corresponding respectively to the at least three coupling ends, and a modulator switch to receive a single modulator switching signal input. Methods may include those used to form and operate such circuits. Additional apparatus, systems, and methods are disclosed.

Claims

1. An integrated circuit chip for use with a Radio Frequency Identification (RFID) tag having an antenna structure with at least three coupling ends for mounting on the chip, the chip comprising:

at least three nodes corresponding respectively to the at least three coupling ends; and

a modulator switch including;

a first antenna transistor having a first switching terminal coupled to a first one of the at least three nodes, a fourth switching terminal, and a first gate terminal,

a second antenna transistor having a second switching terminal coupled to a second one of the at least three nodes, a fifth switching terminal, and a second gate terminal, and

a common transistor having a third switching terminal coupled to the fourth and fifth switching terminals, a sixth switching terminal coupled to a third one of the at least three nodes, and a third gate terminal coupled to the first and second gate terminals.

2. The integrated circuit chip of claim 1, wherein the first antenna transistor, the second antenna transistor, and the common transistor are formed as a single device.

3. The integrated circuit chip of claim 1, wherein the first switching terminal comprises a drain, and wherein the third switching terminal comprises a source.

4. The integrated circuit chip of claim 1, wherein the third switching terminal comprises a drain, and wherein the sixth switching terminal comprises a source.

5. The integrated circuit chip of claim 1, further comprising:

a third antenna transistor having a seventh switching terminal coupled to a fourth one of the at least three nodes, an eighth switching terminal coupled to the third, fourth, and fifth switching terminals, and a fourth gate terminal coupled to the first, second, and third gate terminals.

6. The integrated circuit chip of claim 1, comprising:

a grounded antenna terminal to couple to the third one of the at least three nodes.

7. A Radio Frequency Identification (RFID) tag, comprising:

an inlay;

an antenna structure on the inlay that has at least three coupling ends; and

a circuit for driving the antenna structure from the at least three coupling ends, the circuit comprising;

at least three nodes coupled respectively to the at least three coupling ends, a first antenna transistor having a first switching terminal coupled to a first one of the at least three nodes, a fourth switching terminal, and a first gate terminal, a second antenna transistor having a second switching terminal coupled to a second one of the at least three nodes, a fifth switching terminal, and a second gate terminal, and

a common transistor having a third switching terminal coupled to the fourth and fifth switching terminals, a sixth switching terminal coupled to a third one of the at least three nodes, and a third gate terminal coupled to the first and second gate terminals.

8. The RFID tag of claim 7, wherein the first antenna transistor, the second antenna transistor, and the common transistor comprise an integrated modulator formed as a single device.

9. The RFID tag of claim 7, wherein the first switching terminal comprises a drain, and wherein the third switching terminal comprises a source.

10. The RFID tag of claim 7, wherein the third switching terminal comprises a drain, and wherein the sixth switching terminal comprises a source.

11. The RFID tag of claim 7, further comprising:

a third antenna transistor having a seventh switching terminal coupled to a fourth one of the at least three nodes, an eighth switching terminal coupled to the third, fourth, and fifth switching terminals, and a fourth gate terminal coupled to the first, second, and third gate terminals.

12. A method, comprising:

providing schematic-type inputs for the purpose of preparing a layout that embodies the schematic-type inputs, in which, if the layout is incorporated in a tapeout file that is used by mask making machinery as instructions for processing a semiconductor wafer, an integrated circuit will result on the wafer according to the schematic-type inputs, the integrated circuit comprising;

at least three nodes corresponding respectively to the at least three coupling ends; and

a modulator switch including;

a first antenna transistor having a first switching terminal coupled to a first one of the at least three nodes, a fourth switching terminal, and a first gate terminal,

a second antenna transistor having a second switching terminal coupled to a second one of the at least three nodes, a fifth switching terminal, and a second gate terminal, and

a common transistor having a third switching terminal coupled to the fourth and fifth switching terminals, a sixth switching terminal coupled to a third one of the at least three nodes, and a third gate terminal coupled to the first and second gate terminals.

13. The method of claim 12, in which the first antenna transistor, the second antenna transistor, and the common transistor are formed as a single device as a part of the integrated circuit.

14. The method of claim 12, in which the integrated circuit further comprises:

a third antenna transistor having a seventh switching terminal coupled to a fourth one of the at least three nodes, an eighth switching terminal coupled to the third, fourth, and fifth switching terminals, and a fourth gate terminal coupled to the first, second, and third gate terminals.

15. An article comprising a machine-readable memory containing thereon instructions which, if executed by mask making machinery as instructions for processing a semiconductor wafer, an integrated circuit will result on the wafer, comprising:

at least three nodes corresponding respectively to the at least three coupling ends; and

a modulator switch including;

a first antenna transistor having a first switching terminal coupled to a first one of the at least three nodes, a fourth switching terminal, and a first gate terminal,

a second antenna transistor having a second switching terminal coupled to a second one of the at least three nodes, a fifth switching terminal, and a second gate terminal, and

a common transistor having a third switching terminal coupled to the fourth and fifth switching terminals, a sixth switching terminal coupled to a third one of the at least three nodes, and a third gate terminal coupled to the first and second gate terminals.

16. The article of claim 15, in which the first antenna transistor, the second antenna transistor, and the common transistor are formed as a single device as a part of the integrated circuit.

17. The article of claim 15, in which the integrated circuit comprises:

a third antenna transistor having a seventh switching terminal coupled to a fourth one of the at least three nodes, an eighth switching terminal coupled to the third, fourth, and fifth switching terminals, and a fourth gate terminal coupled to the first, second, and third gate terminals.

18. The article of claim 15, in which the integrated circuit comprises:

a grounded antenna terminal to couple to the third one of the at least three nodes.