Non-volatile dual port third dimensional memory
First Claim
1. A memory system, comprising:
- a back-end-of-the-line (BEOL) portion including a non-volatile third dimensional memory array, the non-volatile third dimensional memory array including a memory element, wherein the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage;
a front-end-of-the-line (FEOL) portion including active circuitry, the active circuitry including a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, wherein the transceiver gate is further configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being electrically coupled with the memory element and configured to provide the another voltage; and
a plurality of word lines electrically coupled with the memory element, wherein the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports.
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Accused Products
Abstract
Non-volatile dual port memory with third dimension memory is described, including a non-volatile third dimensional memory array comprising a memory element, the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage, a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, the transceiver gate is configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being coupled to the memory element and configured to provide the another voltage, and a plurality of word lines coupled to the memory element, the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports.
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Citations
31 Claims
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1. A memory system, comprising:
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a back-end-of-the-line (BEOL) portion including a non-volatile third dimensional memory array, the non-volatile third dimensional memory array including a memory element, wherein the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage; a front-end-of-the-line (FEOL) portion including active circuitry, the active circuitry including a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, wherein the transceiver gate is further configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being electrically coupled with the memory element and configured to provide the another voltage; and a plurality of word lines electrically coupled with the memory element, wherein the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A non-volatile system, comprising:
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a back-end-of-the-line (BEOL) portion including a third dimensional memory array including a memory element, wherein the memory element is configured to change a resistive state when a voltage is applied, the voltage being measured between a first terminal and a second terminal; a front-end-of-the-line (FEOL) portion including active circuitry, the active circuitry including an access transistor configured to gate the voltage and to provide access to the memory element, wherein the access transistor is configured to receive another voltage from a bit line and a bit bar line, wherein the bit line and the bit bar line are electrically coupled with the memory element, the another voltage indicating a data bit to be stored in the memory element, the data bit being determined by evaluating a voltage difference; and a plurality of word lines electrically coupled with the memory element, wherein the plurality of word lines are configured to provide two or more ports substantially simultaneous access to the third dimensional memory array, wherein the substantially simultaneous access occurs randomly. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A non-volatile memory system, comprising:
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a back-end-of-the-line (BEOL) third dimensional rewritable memory array including a memory element, wherein the memory element comprises a plurality of word lines electrically coupled with a row address decoder, wherein the memory element is configured to receive a read voltage and to pass the read voltage to a sense amplifier; a write driver configured to conduct an incoming voltage to access the memory element, wherein the write driver is configured to provide the incoming voltage to enable a bit line and a bit bar line to receive a voltage pulse, wherein the voltage pulse is configured to enable a data bit to be stored in the memory element, wherein the data bit is determined by evaluating a voltage difference measured between a first terminal and a second terminal; a read transistor configured to pass the read voltage to the memory element, wherein the read transistor is enabled by the row address decoder; and a plurality of columns configured to conduct another read voltage to the memory array, the another read voltage being used to read another data bit by evaluating another voltage difference between the first terminal and the second terminal, and the plurality of columns being further configured to conduct another voltage pulse to write data to the third dimensional rewritable memory array by changing a resistive state of the memory element, and wherein active circuitry electrically coupled with the BEOL third dimensional rewritable memory array comprises front-end-of-the-line (FEOL) circuitry fabricated on a substrate the BEOL third dimensional rewritable memory is positioned over and is in contact with. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification