Non-volatile dual port third dimensional memory

• US 8,295,073 B2
• Filed: 11/23/2009
• Issued: 10/23/2012
• Est. Priority Date: 01/30/2009
• Status: Active Grant

• Current Assignee: III Holdings 1, LLC
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Norman, Robert
• Primary Examiner(s): Luu, Pho M
• Assistant Examiner(s): BUI, THA-O H
• Application Number:
  US12/592,319
• Publication Number:
  US 20100195362A1
• Time in Patent Office: 1,065 Days
• Field of Search: 365/51, 365/131, 365/148, 365/158, 365/163, 365/171, 365/173
• US Class Current: 365/148
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Non-volatile dual port memory with third dimension memory is described, including a non-volatile third dimensional memory array comprising a memory element, the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage, a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, the transceiver gate is configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being coupled to the memory element and configured to provide the another voltage, and a plurality of word lines coupled to the memory element, the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports.

Claims

1. A memory system, comprising:

a back-end-of-the-line (BEOL) portion including a non-volatile third dimensional memory array, the non-volatile third dimensional memory array including a memory element, wherein the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage;

a front-end-of-the-line (FEOL) portion including active circuitry, the active circuitry including a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, wherein the transceiver gate is further configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being electrically coupled with the memory element and configured to provide the another voltage; and

a plurality of word lines electrically coupled with the memory element, wherein the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports.

2. The memory system of claim 1, wherein the substantially simultaneous access occurs randomly.

3. The memory system of claim 1, wherein the non-volatile third dimensional memory array uses two terminals.

4. The memory system of claim 1, wherein the non-volatile third dimensional memory array is vertically stacked.

5. The memory system of claim 1, wherein the non-volatile third dimensional memory array comprises a cross-point architecture.

6. The memory system of claim 1, wherein the non-volatile third dimensional memory array further comprises an access port, the access port being associated with the transceiver gate.

7. The memory system of claim 1, wherein the memory array further comprises two or more access ports associated with the non-volatile third dimensional memory.

8. The memory system of claim 1, wherein each memory element is a two-terminal memory element that is included in and is electrically in series with a two-terminal memory cell.

9. A non-volatile system, comprising:

a back-end-of-the-line (BEOL) portion including a third dimensional memory array including a memory element, wherein the memory element is configured to change a resistive state when a voltage is applied, the voltage being measured between a first terminal and a second terminal;

a front-end-of-the-line (FEOL) portion including active circuitry, the active circuitry including an access transistor configured to gate the voltage and to provide access to the memory element, wherein the access transistor is configured to receive another voltage from a bit line and a bit bar line, wherein the bit line and the bit bar line are electrically coupled with the memory element, the another voltage indicating a data bit to be stored in the memory element, the data bit being determined by evaluating a voltage difference; and

a plurality of word lines electrically coupled with the memory element, wherein the plurality of word lines are configured to provide two or more ports substantially simultaneous access to the third dimensional memory array, wherein the substantially simultaneous access occurs randomly.

10. The non-volatile system of claim 9, wherein the memory element is configured to change from a first resistive state to a second resistive state.

11. The non-volatile system of claim 9, wherein the third dimensional memory array uses two or more terminals.

12. The non-volatile system of claim 9, wherein the third dimensional memory array is vertically stacked.

13. The non-volatile system of claim 9, wherein the third dimensional memory array is cross-point accessible.

14. The non-volatile system of claim 9, wherein the third dimensional memory array comprises two or more transceiver gates associated with each access port.

15. The non-volatile system of claim 9, wherein the third dimensional memory array uses two or more access ports associated with the memory element.

16. The non-volatile system of claim 9, wherein the third dimensional memory array is configured to conduct a further voltage across the memory element during a read operation, wherein the read operation is non-destructive.

17. The non-volatile system of claim 9, wherein the third dimensional memory array is configured to conduct the voltage and the another voltage across the memory element during a write operation, wherein the write operation is not preceded by an erase operation.

18. The memory system of claim 9, wherein each memory element is a two-terminal memory element that is included in and is electrically in series with a two-terminal memory cell.

19. A non-volatile memory system, comprising:

a back-end-of-the-line (BEOL) third dimensional rewritable memory array including a memory element, wherein the memory element comprises a plurality of word lines electrically coupled with a row address decoder, wherein the memory element is configured to receive a read voltage and to pass the read voltage to a sense amplifier;

a write driver configured to conduct an incoming voltage to access the memory element, wherein the write driver is configured to provide the incoming voltage to enable a bit line and a bit bar line to receive a voltage pulse, wherein the voltage pulse is configured to enable a data bit to be stored in the memory element, wherein the data bit is determined by evaluating a voltage difference measured between a first terminal and a second terminal;

a read transistor configured to pass the read voltage to the memory element, wherein the read transistor is enabled by the row address decoder; and

a plurality of columns configured to conduct another read voltage to the memory array, the another read voltage being used to read another data bit by evaluating another voltage difference between the first terminal and the second terminal, and the plurality of columns being further configured to conduct another voltage pulse to write data to the third dimensional rewritable memory array by changing a resistive state of the memory element, and

wherein active circuitry electrically coupled with the BEOL third dimensional rewritable memory array comprises front-end-of-the-line (FEOL) circuitry fabricated on a substrate the BEOL third dimensional rewritable memory is positioned over and is in contact with.

20. The non-volatile memory system of claim 19, wherein the memory element is configured to conduct the read voltage, the read voltage being conducted over the bit line to the sense amplifier.

21. The non-volatile memory system of claim 19, wherein the third dimensional rewritable memory array further comprises a column address decoder and an output driver.

22. The non-volatile memory system of claim 19, wherein the sense amplifier is electrically coupled with a resistive reference cell.

23. The non-volatile memory system of claim 19, wherein the third dimensional rewritable memory array is configured to provide substantially simultaneous access using two or more ports.

24. The non-volatile memory system of claim 19, wherein the memory element is configured to change the resistive state when a voltage pulse is applied to the memory element.

25. The non-volatile memory system of claim 19, wherein the third dimensional rewritable memory array is configured to provide access to the memory element using two or more ports.

26. The non-volatile memory system of claim 19, wherein the third dimensional rewritable memory array is configured to enable the incoming voltage to access the memory element.

27. The non-volatile memory system of claim 19, wherein the memory element is configured to receive the incoming voltage from the write driver, the write driver being coupled to the bit line and bit bar line.

28. The non-volatile memory system of claim 19, wherein the third dimensional rewriteable memory array is further configured to use with an interface protocol to emulate DRAM-type memory.

29. The non-volatile memory system of claim 19, wherein the third dimensional rewriteable memory array is further configured to use with an interface protocol to emulate SRAM-type memory.

30. The non-volatile memory system of claim 19, wherein the third dimensional rewriteable memory array is further configured to use with an interface protocol to emulate Flash-type memory.

31. The memory system of claim 19, wherein each memory element is a two-terminal memory element that is included in and is electrically in series with a two-terminal memory cell.