Resistive memory and method for controlling operations of the same
First Claim
1. A method for controlling operations of a resistive memory, the resistive memory having a first memory layer, a second memory layer and a medium layer formed between the first memory layer and the second memory layer, the method comprising at least a step of:
- (a) measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance;
wherein the step (a) comprises;
measuring the resistance as a first resistance by applying a first voltage to the resistive memory;
determining that the state of the resistive memory is the first state when the first resistance is equal to a predetermined value;
when the first resistance is different from the predetermined value, measuring the resistance as a second resistance by applying a second voltage to the resistive memory; and
determining that the state of the resistive memory is the second state when the second resistance is equal to the first resistance, or determining that the state of the resistive memory is the third state when the second resistance is not equal to the first resistance.
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Accused Products
Abstract
A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.
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Citations
16 Claims
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1. A method for controlling operations of a resistive memory, the resistive memory having a first memory layer, a second memory layer and a medium layer formed between the first memory layer and the second memory layer, the method comprising at least a step of:
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(a) measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance; wherein the step (a) comprises; measuring the resistance as a first resistance by applying a first voltage to the resistive memory; determining that the state of the resistive memory is the first state when the first resistance is equal to a predetermined value; when the first resistance is different from the predetermined value, measuring the resistance as a second resistance by applying a second voltage to the resistive memory; and determining that the state of the resistive memory is the second state when the second resistance is equal to the first resistance, or determining that the state of the resistive memory is the third state when the second resistance is not equal to the first resistance. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A resistive memory, comprising:
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a first solid electrolyte; a second solid electrolyte; an oxidizable electrode, formed between the first solid electrolyte and the second solid electrolyte; a composing layer having two silicon oxide spacers and a tungsten layer, wherein the tungsten layer is formed between the two silicon oxide spacers, and the second solid electrolyte is formed between the oxidizable electrode and the composing layer; a titanium nitride layer; an inter-metal dielectric (IMD) layer; and a substrate; wherein the first solid electrolyte and the second solid electrolyte are made of transition metal oxide or materials containing at least one chalcogenide element; wherein the titanium nitride layer is formed between the composing layer and the IMD layer, and the IMD layer is formed between the titanium nitride layer and the substrate. - View Dependent Claims (12)
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13. A resistive memory, comprising:
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a first barrier layer; a second barrier layer; a metal oxide layer, formed between the first barrier layer and the second barrier layer; two silicon oxide spacers; a first electrode; a second electrode; an inter-metal dielectric (IMD) layer; and a substrate; wherein the two silicon oxide spacers are contacted with the metal oxide layer and formed between the first barrier layer and the second barrier layer, the first electrode is formed on the first barrier layer, the second electrode is formed between the second barrier layer and the IMD layer, and the IMD layer is formed between the second electrode and the substrate; wherein a first active region is between the first barrier layer and the metal oxide layer, and a second active region is between the second barrier layer and the metal oxide layer. - View Dependent Claims (14, 15, 16)
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Specification