Gate level reconfigurable magnetic logic

• US 8,295,082 B2
• Filed: 08/15/2008
• Issued: 10/23/2012
• Est. Priority Date: 08/15/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chua-Eoan, Lew G., Zhu, Xiaochun, Zhu, Zhi
• Primary Examiner(s): Ismail, Shawki S
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US12/192,386
• Publication Number:
  US 20100039136A1
• Time in Patent Office: 1,530 Days
• Field of Search: 326 37- 41, 365/171
• US Class Current: 365/171
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/18 using galvano-magnetic devices, e.g. Hall-effect devices

Abstract

A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation switch in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal based on the programmed states of the memory circuits. A sensor is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power.

Claims

1. A non-volatile re-programmable gate logic comprising:

a non-volatile resistance-based memory cell comprising a sensor circuit configured to receive a selected threshold voltage and to output a first logical signal corresponding to a first logical functionality of the non-volatile resistance-based memory cell in response to the selected threshold voltage being a first threshold voltage, and to output a second logical signal corresponding to a second logical functionality of the non-volatile resistance-based memory cell in response to the selected threshold voltage being a second threshold voltage; and

the sensor circuit configured to output a selected one or more logical signal based on a detected output signal and a selected threshold reference signal level.

2. The gate logic of claim 1, wherein the non-volatile resistance-based memory cell comprises:

a plurality of reconfigurable non-volatile resistance-based junction circuits, each non-volatile reconfigurable resistance-based junction circuit being configured to receive an input logic signal; and

an evaluation switch in series with the plurality of reconfigurable non-volatile resistance-based junction circuits, wherein the evaluation switch is configured to provide an output signal based on a configuration of resistance states of the plurality of reconfigurable non-volatile resistance-based junction circuits.

3. The gate logic of claim 2, wherein the evaluation switch is a one or more transistors in a selected combination of series and/or parallel.

4. The gate logic of claim 2, wherein the evaluation switch is a one or more reconfigurable non-volatile resistance-based junction circuits in the selected combination of series and/or parallel.

5. The gate logic of claim 2, wherein the evaluation switch is a one or more transistors and/or a one or more non-volatile reconfigurable resistance-based junction circuits in the selected combination of series and/or parallel.

6. The gate logic of claim 2, wherein the reconfigurable non-volatile resistance-based junction circuits comprise one or more of phase-change random access memory (PC-RAM) circuits, resistance-based random access memory (R-RAM) circuits, magnetoresistance random access memory (MRAM) circuits and spin transfer torque magnetoresistance tunnel junction MRAM (STT MTJ MRAM) circuits.

7. The gate logic of claim 6, wherein the STT MTJ MRAM circuit comprises:

a magnetic tunnel junction (MTJ); and

a first metal interconnect configured to provide a bit line write signal and/or an input read signal to the MTJ, wherein the bit line write signal configures a resistance state of the MTJ and the input read signal is applied to determine the resistance state.

8. The gate logic of claim 7, further comprising a switch operatively coupled to the MTJ and a source line to permit current to flow through the MTJ for a read and/or write operation.

9. The gate logic of claim 7, wherein the MTJ comprises:

a top electrode in communication with the metal interconnect;

a free magnetization layer adjacent to the top electrode;

a tunnel barrier layer adjacent to the free magnetization layer;

a fixed magnetization layer adjacent to the tunnel barrier; and

a bottom electrode adjacent the fixed magnetization layer in communication with the switch.

10. The gate logic of claim 2, wherein the evaluation switch comprises:

a second metal interconnect in series communication with the plurality of reconfigurable non-volatile resistance-based junction circuits; and

a switching element having a source electrode in communication with the second metal interconnect, a gate electrode configured to receive a control signal to change a resistance state of a conductive path of the switching element, and a source electrode, wherein the switching element is selected from at least a transistor, an MRAM cell and an STT MTJ MRAM cell.

11. The gate logic of claim 10, in which the sensor circuit is configured to detect the voltage at the second metal interconnect, and output the selected one or more logical signals based on the detected voltage and the selected threshold voltage.

12. The gate logic of claim 11, wherein the output signals of the sensor comprise a logical 1 and/or a logical 0.

13. The apparatus of claim 1, integrated into one of a cell phone, handheld personal communication system unit, portable data unit, personal digital assistant and meter reading equipment.

14. A write method of reconfiguring a non-volatile re-programmable gate logic comprising a non-volatile resistance-based memory cell, wherein the non-volatile resistance-based memory cell comprises a sensor circuit coupled to a plurality of reconfigurable non-volatile resistance-based junction circuits, each non-volatile reconfigurable resistance-based junction circuit being configured to receive a separate input logic signal, the method comprising:

applying a write input signal to each of the plurality of reconfigurable non-volatile resistance-based junction circuits, wherein a direction of current of the write input signal determines a resistance state of the non-volatile resistance-based junction circuit; and

controlling a threshold voltage of the sensor circuit, the threshold voltage determining a selected logic function of the non-volatile resistance-based memory cell from a plurality of selectable logic functions.

15. The write method of claim 14, further comprising selecting the direction of the write input signals to determine a set of resistance states of each reconfigurable non-volatile resistance-based junction circuit, the resistance states corresponding to the selected logic function.

16. The method of claim 14, further comprising integrating the non-volatile resistance-based memory cell into one of a cell phone, handheld personal communication system unit, portable data unit, personal digital assistant and meter reading equipment.

17. A method of operating a non-volatile re-programmable gate logic comprising a non-volatile resistance-based memory cell, wherein the non-volatile resistance-based memory cell comprises a plurality of reconfigurable non-volatile resistance-based junction circuits, the method comprising:

applying a read input signal to each of the plurality of reconfigurable non-volatile resistance-based junction circuits, wherein the read input signal is less than a magnitude of a write input signal and too small to change a resistance state of the non-volatile resistance-based junction circuit;

reading an output signal based on a configuration of resistance states of the plurality of non-volatile reconfigurable resistance-based junction circuits at an interconnection between the reconfigurable non-volatile resistance-based junction circuits and an evaluation switch;

detecting the output signal by a sensor circuit operatively coupled to the interconnection, the sensor circuit receiving a selected threshold reference signal level, the selected threshold reference signal determining a selected logic function from a plurality of selectable logic functions; and

outputting a selected one or more logical signals based on the detected output signal and the selected threshold reference signal level.

18. The method of claim 17, wherein the selected one or more logical signals comprise a logical 1 and/or a logical 0.

19. The method of claim 17, further comprising integrating the non-volatile resistance-based memory cell into one of a cell phone, handheld personal communication system unit, portable data unit, personal digital assistant and meter reading equipment.

20. A non-volatile re-programmable gate logic comprising:

a non-volatile resistance-based memory cell comprising means for receiving a selected threshold voltage and means for outputting a first logical signal corresponding to a first logical functionality of the non-volatile resistance-based memory cell in response to the selected threshold voltage being a first threshold voltage, and means for outputing a second logical signal corresponding to a second logical functionality of the non-volatile resistance-based memory cell in response to the selected threshold voltage being a second threshold voltage.

21. The apparatus of claim 20, integrated into one of a cell phone, handheld personal communication system unit, portable data unit, personal digital assistant and meter reading equipment.