Non-volatile memory device having vertical structure and method of operating the same

• US 8,295,089 B2
• Filed: 02/02/2010
• Issued: 10/23/2012
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Jae-hun, Kim, Han-soo, Cho, Won-seok, Jang, Jae-hoon, Shim, Sun-il
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US12/658,072
• Publication Number:
  US 20100195395A1
• Time in Patent Office: 994 Days
• Field of Search: 365/185.17, 365/185.11
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Claims

1. A non-volatile memory device having a vertical structure, the non-volatile memory device comprising:

a substrate;

a semiconductor pole formed on the substrate to extend vertically with respect to the substrate;

a NAND string formed on the substrate to extend vertically with respect to the substrate and along sidewalls of the semiconductor pole, the NAND string comprising a plurality of memory cells arranged in series and at least one pair of first selection transistors adjacent to the plurality of memory cells;

a plurality of word lines coupled to the plurality of memory cells of the NAND string; and

a first selection line commonly coupled to the at least one pair of first selection transistors of the NAND string.

2. The non-volatile memory device of claim 1, further comprising:

a bit line connected to a first end of the NAND string; and

a common source line connected to a second end of the NAND string proximate to the substrate and opposite to the bit line.

3. The non-volatile memory device of claim 2, wherein the at least one pair of first selection transistors is arranged between the bit line and the plurality of memory cells.

4. The non-volatile memory device of claim 2, wherein the at least one pair of first selection transistors is arranged between the common source line and the plurality of memory cells.

5. The non-volatile memory device of claim 1, wherein the NAND string further comprises at least one pair of second selection transistors adjacent to a second end of the plurality of memory cells and opposite to the at least one pair of first selection transistors.

6. The non-volatile memory device of claim 5, further comprising a second selection line commonly connected to the at least one pair of second selection transistors of the NAND string.

7. The non-volatile memory device of claim 1, wherein the plurality of memory cells comprise control gate electrodes on the sidewall of the semiconductor pole, and

the at least one pair of first selection transistors comprise first gate electrodes on the sidewall of the semiconductor pole.

8. The non-volatile memory device of claim 7, wherein the difference between a gate length of each of the control gate electrodes and a gate length of each of the first gate electrodes is in a range of about 0 nm to 10 nm.

9. The non-volatile memory device of claim 1, wherein the NAND string further comprises at least one pair of second selection transistors adjacent to the plurality of memory cells and opposite to the at least one pair of first selection transistors.

10. The non-volatile memory device of claim 9, further comprising a second selection line commonly coupled to the at least one pair of second selection transistors of the NAND string.