Processor instruction cache with dual-read modes

• US 8,295,110 B2
• Filed: 09/26/2011
• Issued: 10/23/2012
• Est. Priority Date: 10/13/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Su, Jason T., Chen, Hong-Yi, Sheu, Jason, Tjeng, Jensen
• Primary Examiner(s): Nguyen, Tuan T
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US13/245,551
• Publication Number:
  US 20120014196A1
• Time in Patent Office: 393 Days
• Field of Search: 365/203, 365/233.1, 365/233.11, 36523316-23319, 365/238.5, 365/239, 712/205, 711/118, 711/125
• US Class Current: 365/203
• CPC Class Codes: G06F 12/0882 Page mode
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 2207/2281 Timing of a read operation
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.

Claims

1. A processor comprising:

a cache memory comprising an array of memory cells;

a decoder configured to (i) generate a first word line signal to access first instructions stored in a first word line of the array of memory cells, and (ii) generate a second word line signal to access second instructions stored in the first word line or a second word line of the array of memory cells;

a precharge circuit configured to (i) precharge first bit lines connected to the first word line during a first precharge event and prior to accessing the first instructions, and (ii) precharge the first bit lines during a second precharge event and prior to accessing the second instructions, wherein the second precharge event is subsequent to the first precharge event;

a control module configured to, during the first precharge event, adjust a rate of a clock signal from a first rate to a second rate; and

an amplifier module configured to

access the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and

access the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.

2. The processor of claim 1, wherein the control module is configured to delay the second precharge event based on the adjustment in the rate of the clock signal.

3. The processor of claim 1, wherein the second precharge event is initiated within a predetermined period prior to the second word line signal.

4. The processor of claim 1, wherein the control module is configured to:

begin precharging, via the precharge circuit, the first bit lines to access the first instructions during a first clock cycle when the clock signal is generated at the first rate; and

delay precharging, via the precharge circuit, the first bit lines to access the second instructions until after a second clock cycle when the clock signal is generated at the second rate,

wherein the second clock cycle is generated consecutively after the first clock cycle.

5. The processor of claim 4, wherein:

the first word line signal is generated during the first clock cycle; and

the second word line signal is generated during the second clock cycle.

6. The processor of claim 1, wherein:

the clock signal includes a first clock cycle, a second clock cycle, and a third clock cycle;

the first clock cycle, the second clock cycle and the third clock cycle are generated consecutively with the second clock cycle being generated between the first clock cycle and the third clock cycle; and

the control module is configured to

begin precharging, via the precharge circuit, the first bit lines to access the first instructions subsequent to a rising edge of the first clock cycle when the clock signal is generated at the first rate, and

delay precharging, via the precharge circuit, the first bit lines to access the second instructions until after a rising edge of the third clock cycle when the clock signal is generated at the second rate.

7. The processor of claim 6, wherein the rate of the clock signal is adjusted from the first rate to the second rate during the second clock cycle.

8. The processor of claim 6, wherein the control module is configured to, via the precharge circuit:

precharge the first bit lines to access the first instructions a first period after a first falling edge of a first word line cycle of the first word line signal; and

precharge the first bit lines to access the second instructions a second period after a second falling edge of a second word line cycle of the second word line signal,

wherein the second word line cycle is generated consecutively after the first word line cycle, and

wherein the second period is longer than the first period.

9. The processor of claim 1, wherein:

the first precharge event is performed a first period after a previous precharge event;

the second precharge event is performed a second period after the first precharge event;

the second period is longer than the first period;

the first precharge event is performed consecutively after the previous precharge event; and

the second precharge event is performed consecutively after the first precharge event.

10. The processor of claim 1, wherein:

a first voltage potential of a first one of the first bit lines is equal to a second voltage potential of a second one of the first bit lines during the first precharge event;

a difference between the first voltage potential and the second voltage potential increases subsequent to the first precharge event; and

the first voltage potential remains different than the second voltage potential for a separation period between the first precharge event and the second precharge event, wherein a duration of the separation period is based on the second rate.

11. The processor of claim 1, wherein:

a bit line separation between a first one of the first bit lines and a second one of the first bit lines during the first precharge event is zero;

the bit line separation is greater than zero subsequent to the first precharge event;

the bit line separation remains greater than zero for a separation period between the first precharge event and the second precharge event, wherein a duration of the separation period is based on the second rate; and

the bit line separation is equal to zero during the second precharge event.

12. The processor of claim 1, wherein:

the first word line signal defines an extended period to increase separation between two of the first bit lines; and

the extended period is based on a predetermined number of read cycles.

13. The processor of claim 1, wherein the control module is configured to:

generate a third word line signal to access third instructions stored in the second word line of the array of memory cells; and

precharge, via the precharge circuit, second bit lines of the array of the memory cells connected to the second word line prior to accessing the third instructions.

14. The processor of claim 1, wherein the control module is configured to, when performing a sequential read:

enable the first word line to access the first instructions;

disable the first word line; and

maintain the first word line in a disabled state when accessing the second instructions in the first word line.

15. The processor of claim 1, wherein the control module is configured to, when performing a sequential read:

generate a first word line pulse associated with the first word line signal for a first access cycle of the first bit lines; and

refrain from generating a second word line pulse associated with the second word line signal for a second access cycle of the bit lines, wherein the second word line signal is generated to access the first word line.

16. The processor of claim 1, wherein the control module is configured to:

determine bit line separation based on a number of access cycles to be performed along the first word line; and

precharge the first bit lines to provide the bit line separation when accessing the first instructions and the second instructions.

17. The processor of claim 1, wherein the control module is configured to perform:

a first sequential read to access the first instructions;

a second sequential read in response to a branch instruction to access third instructions stored in the array of memory cells, wherein the third instructions are stored in memory cells of the array of memory cells connected to a third word line; and

a third sequential read in response to a return instruction to access fourth instructions stored in the array of memory cells, wherein the fourth instructions are stored in memory cells of the array of memory cells connected to the second word line, and wherein the second word line is between the first word line and the third word line.

18. A method comprising:

generating a first word line signal to access first instructions stored in a first word line of an array of memory cells of a cache memory,

generating a second word line signal to access second instructions stored in the first word line or a second word line of the array of memory cells,

precharging first bit lines connected to the first word line during a first precharge event and prior to accessing the first instructions,

precharging the first bit lines during a second precharge event and prior to accessing the second instructions, wherein the second precharge event is subsequent to the first precharge event,

adjusting a rate of a clock signal from a first rate to a second rate during the first precharge event,

accessing the first instructions in response to the first word line signal and based on the clock signal at the first rate, and

accessing the second instructions in response to the second word line signal and based on the clock signal at the second rate.

19. The method of claim 18, further comprising:

beginning precharging the first bit lines to access the first instructions during a first clock cycle when the clock signal is generated at the first rate; and

delaying precharging the first bit lines to access the second instructions until after a second clock cycle when the clock signal is generated at the second rate,

wherein

the second clock cycle is generated consecutively after the first clock cycle,

the first word line signal is generated during the first clock cycle, and

the second word line signal is generated during the second clock cycle.

20. The method of claim 18, further comprising:

beginning precharging the first bit lines to access the first instructions subsequent to a rising edge of a first clock cycle when the clock signal is generated at the first rate; and

delaying precharging the first bit lines to access the second instructions until after a rising edge of a third clock cycle when the clock signal is generated at the second rate,

wherein

the clock signal includes the first clock cycle, a second clock cycle, and the third clock cycle,

the first clock cycle, the second clock cycle and the third clock cycle are generated consecutively with the second clock cycle being generated between the first clock cycle and the third clock cycle,

the first bit lines are precharged to access the first instructions a first period after a first falling edge of a first word line cycle of the first word line signal,

the first bit lines are precharged to access the second instructions a second period after a second falling edge of a second word line cycle of the second word line signal,

the second word line cycle is generated consecutively after the first word line cycle, and

the second period is longer than the first period.