Method and system for implementing multi-controller systems

• US 8,296,527 B2
• Filed: 11/19/2009
• Issued: 10/23/2012
• Est. Priority Date: 11/19/2009
• Status: Active Grant

• Current Assignee: GE Fanuc Intelligent Platforms Incorporated (Fanuc Corporation)
• Original Assignee: GE Intelligent Platforms Incorporated (Emerson Electric Company)
• Inventors: Xu, Yan Hua, Reitzel, Mark, Simons, Jerry, Walsh, Terrance John
• Primary Examiner(s): Farrokh, Hashem
• Application Number:
  US12/622,142
• Publication Number:
  US 20110119453A1
• Time in Patent Office: 1,069 Days
• Field of Search: 711/148, 714/4.2
• US Class Current: 711/148
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 12/084 with a shared cache

Abstract

A method for implementing a high-availability system that includes a plurality of controllers that each includes a shared memory. The method includes storing in the shared memory, by each controller, status data related to each of a plurality of failure modes, and calculating, by each controller, an availability score based on the status data. The method also includes determining, by each controller, one of the plurality of controllers having a highest availability score, and identifying the one of the plurality of controllers having the highest availability score as a master controller.

Claims

1. A method for implementing a high-availability system that includes a plurality of controllers that each includes a shared memory, said method comprising:

storing in the shared memory, by each controller, status data related to each of a plurality of failure modes;

calculating, by each controller, an availability score based on the status data associated, and a priority of each failure mode;

determining, by each controller, one of the plurality of controllers having a highest availability score; and

identifying the one of the plurality of controllers having the highest availability score as a master controller.

2. A method in accordance with claim 1, wherein storing status data comprises storing status data in a portion of the shared memory associated with each controller.

3. A method in accordance with claim 2, further comprising storing a plurality of parameters and a plurality of default values in a separate portion of the shared memory.

4. A method in accordance with claim 2, wherein determining one of the plurality of controllers having a highest availability score comprises scanning the portion of the shared memory associated with each of the plurality of controllers.

5. A method in accordance with claim 1, wherein identifying one of the plurality of controllers as a master controller comprises storing an indicator in a portion of the shared memory associated with the master controller.

6. A high-availability automation system comprising:

a plurality of input/output (I/O) modules; and

a plurality of controllers coupled to each of said plurality of I/O modules via at least one first network, each controller comprising;

a memory comprising a plurality of memory portions each associated with one of said plurality of controllers, each memory portion configured to store data related to each of a plurality of failure modes; and

at least one processor coupled to said memory, said processor configured to;

receive the data related to the plurality of failure modes;

store the data into one of said memory portions;

calculate an availability score based on the data;

periodically scan each controller to receive the availability score of each controller;

identify as a master controller one of said plurality of controllers having a highest availability score; and

store an indicator into one of said memory portions associated with the master controller.

7. A high-availability automation system in accordance with claim 6, wherein said at least one processor of the master controller is configured to synchronize each scan.

8. A high-availability automation system in accordance with claim 6, wherein said plurality of controllers are interconnected via at least one second network.

9. A high-availability automation system in accordance with claim 8, wherein at least a portion of the plurality of failure modes relate to communications between each controller via said at least one second network.

10. A high-availability automation system in accordance with claim 6, wherein at least a portion of the plurality of failure modes relate to communications between each controller and each I/O module.

11. A high-availability automation system in accordance with claim 6, wherein said plurality of controllers each includes a unique identifier.

12. A high-availability automation system in accordance with claim 11, wherein each of said plurality of memory portions is associated with a respective identifier of one of said plurality of controllers.

13. A high-availability automation system in accordance with claim 6, wherein said at least one processor of the master controller is configured to store a sequence number in one of said plurality of memory portions associated with the master controller.

14. A high-availability automation system in accordance with claim 13, wherein each controller is configured to communicate with each I/O module via said at least one first network, and wherein each I/O module is configured to execute only those communications that include the sequence number.

15. One or more computer-readable storage media having computer-executable components for implementing a high-availability system that includes a plurality of controllers that each includes a shared memory, said components comprising:

a storage component that when executed by at least one processor causes the at least one processor to store in the shared memory of each controller status data related to each of a plurality of failure modes;

an availability component that when executed by the at least one processor causes the at least one processor to;

calculate an availability score for each controller, based on the status data, and a priority of each failure mode; and

determine an identity of one of the controllers having a highest availability score; and

a master controller component that when executed by the at least one processor causes the at least one processor to identify the controller having the highest availability score as a master controller.

16. One or more computer-readable storage media in accordance with claim 15, wherein the storage component stores status data in a portion of the shared memory associated with each controller.

17. One or more computer-readable storage media in accordance with claim 15, wherein the storage component stores a plurality of parameters and a plurality of default values in a separate portion of the shared memory.