Method for fabrication of a semiconductor device and structure

• US 8,298,875 B1
• Filed: 03/06/2011
• Issued: 10/30/2012
• Est. Priority Date: 03/06/2011
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Lim, Paul
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/041,404
• Time in Patent Office: 604 Days
• Field of Search: 438/141, 438/529, 257/E21.4, 257/E21.536, 257/E21.615
• US Class Current: 438/141
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/0823 including vertical bipolar transistors only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A method to fabricate a junction-less transistor comprising: forming at least two regions of semiconductor doping; first region with a relatively high level of dopant concentration and second region with at least 1/10 lower dopant concentration, and etching away a portion of said first region for the formation of the transistor gate.

Claims

1. A method to fabricate a junction-less transistor comprising:

forming a transistor body with variable doping, said body comprising a first portion of high dopant concentration and a second portion of at least 1/10 less dopant concentration, and then a transistor channel length is defined by an etch step,

wherein said etch step removes regions of at least one of said portions, and

said first portion and said second portion are of the same dopant type, and

said transistor body comprises source, drain, and channel of said junction-less transistor.

2. A method according to claim 1 comprising layer transfer.

3. A method according to claim 1 wherein said transistor is on top of a fabric comprising one or more horizontal interconnection layers comprising aluminum or copper.

4. A method according to claim 1 wherein said transistor is part of a monolithic 3D IC.

5. A method according to claim 1 wherein said etch step comprises forming a transistor gate.

6. A method according to claim 4, wherein said transistor gate is a multi-sided gate.

7. A method according to claim 1 wherein said transistor body with variable doping comprises a dopant gradient as the doping changes from high concentration to low concentration.

8. A method according to claim 1 further comprising source and drain transistor contacts wherein said contacts are made to said first portion of high dopant concentration.

9. A method accordingly to claim 1 wherein said first portion overlays said second portion.

10. A method according to claim 1 wherein said transistor body with variable doping is formed prior to layer transfer.

11. A method to fabricate a junction-less transistor comprising:

forming a transistor body with variable doping, said body comprising a first portion of high dopant concentration and a second portion of at least 1/10 less dopant concentration,

wherein said first portion overlays said second portion, and

a transistor channel length is defined by an etch step, and

said first portion and said second portion are of the same dopant type, and

said transistor body comprises source, drain, and channel of said junction-less transistor.

12. A method according to claim 11 comprising layer transfer.

13. A method according to claim 11 wherein said transistor is on top of a fabric comprising one or more horizontal interconnection layers comprising aluminum or copper.

14. A method according to claim 11 wherein said transistor is part of a monolithic 3D IC.

15. A method according to claim 11 wherein said etch step comprises forming a transistor gate.

16. A method according to claim 15 wherein said transistor gate is a multi-sided gate.

17. A method according to claim 11 wherein said transistor body with variable doping comprises a dopant gradient as the doping changes from high concentration to low concentration.

18. A method according to claim 11 further comprising source and drain transistor contacts wherein said contacts are made to said first portion of high dopant concentration.

19. A method according to claim 11 wherein said transistor body with variable doping is formed prior to layer transfer.