Process of forming an electronic device including a trench and a conductive structure therein

• US 8,298,889 B2
• Filed: 12/10/2008
• Issued: 10/30/2012
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Roig-Guitart, Jaume, Moens, Peter, Tack, Marnix
• Primary Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US12/331,985
• Publication Number:
  US 20100140698A1
• Time in Patent Office: 1,420 Days
• Field of Search: None
• US Class Current: 438/242
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Abstract

An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.

Claims

1. A process of forming an electronic device comprising:

providing a workpiece including a first layer, a well region, and a buried doped region, wherein;

the first layer has a primary surface;

the well region lies adjacent to the primary surface; and

the buried doped region is spaced apart from the primary surface and the well region;

forming a first insulating layer over the primary surface;

forming a second insulating layer over the first insulating layer, wherein the second insulating layer has a different composition as compared to the first insulating layer;

forming a trench extending through the well region and towards the buried doped region, wherein;

forming the trench is performed after forming the first and second insulating layers; and

a portion of the well region and a portion of the first layer lie along a sidewall of the trench;

doping the portion of the first layer along the sidewall of the trench after forming the trench to form a sidewall doped region along the sidewall and below the well region, wherein;

a dopant for the sidewall doped region is introduced into the first layer along the sidewall of the trench, wherein the dopant has a conductivity type that is the same as the well region and opposite that of the first layer;

doping the portion of the first layer along the sidewall of the trench is performed using the dopant; and

doping the portion of the first layer comprises performing a tilt angle implant; and

forming an insulating sidewall spacer along the sidewall of the trench;

forming a conductive structure within the trench after forming the insulating sidewall spacer, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region,

wherein the electronic device comprises a transistor that includes a channel region within the well region.

2. The process of claim 1, wherein doping the portion of the first layer comprises ion implanting a dopant at an angle in a range of approximately 20°

to approximately 35°

.

3. The process of claim 1, wherein doping the portion of the first layer comprises ion implanting a dopant at an angle of at least approximately 8°

.

4. The process of claim 1, wherein forming the conductive structure comprises:

depositing a refractory metal-containing material overlying the primary surface and substantially filling a remainder of the trench; and

polishing the refractory metal-containing material to remove a portion of the refractory metal-containing material that overlies the primary surface.

5. The process of claim 1, further comprising planarizing the first insulating layer before forming the second insulating layer.

6. The process of claim 1, further comprising:

forming a source region of the transistor within the well region and adjacent to the primary surface;

forming a well contact region within the well region and adjacent to the primary surface, wherein the well contact region has a higher peak dopant concentration as compared to the well region; and

forming a gate electrode of the transistor that overlies the channel region of the transistor and overlies the first layer over the primary surface, wherein the gate electrode lies completely outside of the trench.

7. The process of claim 1, wherein:

the transistor comprises the first layer, the well region, the buried doped region, the sidewall doped region, and the conductive structure; and

the transistor has an operating voltage of at least approximately 100 volts.

8. A process of forming an electronic device comprising:

providing a workpiece including a first layer, a well region, a well contact region, a source region, a buried doped region, and a gate electrode, wherein;

the first layer has a primary surface;

the well region lies adjacent to the primary surface;

the well contact region lies adjacent to the primary surface and within the well region and has a higher peak doping concentration as compared to the well region;

the source region lies adjacent to the primary surface and within the well region and has a higher peak doping concentration as compared to the well region;

the buried doped region is spaced apart from the primary surface and the well region;

the gate electrode overlies the first layer and the well region;

the first layer, the source region, and the buried doped region have a first conductivity type; and

the well region and the well contact region have a second conductivity type opposite that of the first conductivity type;

etching a trench extending to the buried doped region, wherein portions of the first layer and the well region lie along a sidewall of the trench;

implanting a dopant into first layer along the sidewall of the trench;

depositing an insulating layer into the trench;

anisotropically etching the insulating layer to form a sidewall spacer along the sidewall of the trench;

depositing a conductive layer to fill a remaining portion of the trench;

polishing the conductive layer to form a conductive structure, wherein;

polishing removes a portion of the conductive layer that overlies the source region and the gate electrode; and

the sidewall spacer lies between the conductive structure and the sidewall of the trench; and

forming a first interconnect, a second interconnect, and a third interconnect, wherein;

the first interconnect is electrically connected to the conductive structure;

the second interconnect is electrically connected to the well contact region and the source region; and

the third interconnect is electrically connected to the gate electrode.

9. The process of claim 8, wherein:

the electronic device comprises a transistor;

the transistor comprises the first layer, the well region, the well contact region, the source region, the buried doped region, the gate electrode, a doped region along a sidewall of the trench and including the dopant, sidewall spacer, the conductive structure, and the first, second, and third interconnects; and

the transistor is capable of operating at a voltage difference between the first and second interconnects of at least approximately 100 volts.

10. A process of forming an electronic device comprising:

providing a workpiece including a first layer, a well region, and a buried doped region, wherein;

the first layer has a primary surface;

the well region lies adjacent to the primary surface; and

the buried doped region is spaced apart from the primary surface and the well region;

forming a gate electrode that overlies the well region and the first layer at the primary surface;

forming a source region within the well region and adjacent to the primary surface;

forming a well contact region within the well region and adjacent to the primary surface, wherein the well contact region has a higher peak dopant concentration as compared to the well region;

forming a trench extending towards the buried doped region, wherein a portion of the first layer lies along a sidewall of the trench, and wherein forming the trench is performed after forming the gate electrode;

doping the portion of the first layer along the sidewall of the trench to form a sidewall doped region, wherein;

dopant for the sidewall doped region is introduced into the first layer along the sidewall of the trench;

doping is performed after forming the trench; and

the sidewall doped region is spaced apart from the buried doped region; and

forming a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region.

11. The process of claim 10, wherein doping the portion of the first layer comprises ion implanting a dopant at an angle of at least approximately 8°

.

12. The process of claim 10, wherein doping the portion of the first layer comprises ion implanting a dopant at an angle in a range of approximately 20°

to approximately 35°

.

13. The process of claim 10, doping the portion of the first layer along the sidewall of the trench is performed using a dopant having a conductivity type opposite that of the first layer.

14. The process of claim 10, further comprising forming an insulating sidewall spacer along the sidewall of the trench before forming the conductive structure.

15. The process of claim 10, wherein:

the electronic device comprises a transistor;

the transistor comprises the first layer, the well region, the buried doped region, the sidewall doped region, and the conductive structure; and

the transistor has an operating voltage of at least approximately 100 volts.