Semiconductor device
First Claim
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1. A semiconductor device comprising:
- a first semiconductor layer of a first conductivity type;
a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower first conductivity type impurity concentration than the first semiconductor layer;
a third semiconductor layer of a second conductivity type provided on the second semiconductor layer;
a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer and having a higher first conductivity type impurity concentration than the second semiconductor layer;
a first insulating film provided on an inner wall of each of a plurality of first trenches, the first trenches penetrating through the fourth semiconductor layer and the third semiconductor layer to the second semiconductor layer and extending in a first direction parallel to a surface of the first semiconductor layer;
a gate electrode buried in the each of the plurality of first trenches via the first insulating film;
a second insulating film provided on an inner wall of a second trench having a ring-shaped structure, the second trench penetrating through the fourth semiconductor layer and the third semiconductor layer to the second semiconductor layer and including a portion extending in the first direction, the portion dividing each of the third semiconductor layer and the fourth semiconductor layer between a first region and a second region, the first region including a device region inside, the device region including the gate electrode in a plurality, and the second region surrounding the first region outside;
a third insulating film provided on the fourth semiconductor layer in the first region and the second region, connected to the first insulating film and the second insulating film, and insulating the fourth semiconductor layer from outside;
a gate interconnect layer provided on the third insulating film in the first region, surrounding the device region, and electrically connected to the gate electrode at both ends of the each of the first trenches;
an interlayer insulating film provided on the gate electrode, the gate interconnect layer, the second trench, and the third insulating film and insulating the gate electrode and the gate interconnect layer from outside;
a first electrode provided on a surface of the first semiconductor layer opposite to the second semiconductor layer; and
a second electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer through a first opening and a second opening, the first opening penetrating through the interlayer insulating film, the third insulating film, and the fourth semiconductor layer between adjacent ones of the first trenches, and the second opening penetrating through the interlayer insulating film, the third insulating film, and the fourth semiconductor layer and extending in the first direction between the gate interconnect layer and one of the plurality of first trenches adjacent to the gate interconnect layer in a second direction orthogonal to the first direction,in the second direction, width of the second opening being wider than width of the first opening.
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Abstract
In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower first conductivity type impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type provided on the third semiconductor layer and having a higher first conductivity type impurity concentration than the second semiconductor layer; a first insulating film provided on an inner wall of each of a plurality of first trenches, the first trenches penetrating through the fourth semiconductor layer and the third semiconductor layer to the second semiconductor layer and extending in a first direction parallel to a surface of the first semiconductor layer; a gate electrode buried in the each of the plurality of first trenches via the first insulating film; a second insulating film provided on an inner wall of a second trench having a ring-shaped structure, the second trench penetrating through the fourth semiconductor layer and the third semiconductor layer to the second semiconductor layer and including a portion extending in the first direction, the portion dividing each of the third semiconductor layer and the fourth semiconductor layer between a first region and a second region, the first region including a device region inside, the device region including the gate electrode in a plurality, and the second region surrounding the first region outside; a third insulating film provided on the fourth semiconductor layer in the first region and the second region, connected to the first insulating film and the second insulating film, and insulating the fourth semiconductor layer from outside; a gate interconnect layer provided on the third insulating film in the first region, surrounding the device region, and electrically connected to the gate electrode at both ends of the each of the first trenches; an interlayer insulating film provided on the gate electrode, the gate interconnect layer, the second trench, and the third insulating film and insulating the gate electrode and the gate interconnect layer from outside; a first electrode provided on a surface of the first semiconductor layer opposite to the second semiconductor layer; and a second electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer through a first opening and a second opening, the first opening penetrating through the interlayer insulating film, the third insulating film, and the fourth semiconductor layer between adjacent ones of the first trenches, and the second opening penetrating through the interlayer insulating film, the third insulating film, and the fourth semiconductor layer and extending in the first direction between the gate interconnect layer and one of the plurality of first trenches adjacent to the gate interconnect layer in a second direction orthogonal to the first direction, in the second direction, width of the second opening being wider than width of the first opening. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsTomita, Kouta, Matsuda, Noboru, Ura, Hideyuki
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Primary Examiner(s)Doan, Theresa T
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Application NumberUS13/195,579Publication NumberTime in Patent Office456 DaysField of Search257329-330, 257/341, 257/E29.262, 257/E21.41, 438/270US Class Current257/330CPC Class CodesH01L 29/0653 adjoining the input or outp...H01L 29/0657 characterised by the shape ...H01L 29/0661 specially adapted for alter...H01L 29/0696 of cellular field-effect de...H01L 29/402 Field platesH01L 29/404 Multiple field plate struct...H01L 29/407 Recessed field plates, e.g....H01L 29/41741 for vertical or pseudo-vert...H01L 29/41766 with at least part of the s...H01L 29/42372 characterised by the conduc...H01L 29/7811 with an edge termination st...H01L 29/7813 with trench gate electrode,...
