Isolation structure and device structure including the same
First Claim
1. An isolation structure, comprising:
- a doped semiconductor layer in a trench in a semiconductor substrate, having the same conductivity type as the substrate;
gate dielectric between the doped semiconductor layer and the substrate; and
a diffusion region disposed besides a source/drain (S/D) region in the substrate, formed by dopant diffusion through the gate dielectric from the doped semiconductor layer, wherein the diffusion region has a first conductivity type and the source/drain region has a second conductivity type.
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Abstract
An isolation structure is described, including a doped semiconductor layer disposed in a trench in a semiconductor substrate and having the same conductivity type as the substrate, gate dielectric between the doped semiconductor layer and the substrate, and a diffusion region in the substrate formed by dopant diffusion through the gate dielectric from the doped semiconductor layer. A device structure is also described, including the isolation structure and a vertical transistor in the substrate beside the isolation structure. The vertical transistor includes a first S/D region beside the diffusion region and a second S/D region over the first S/D region both having a conductivity type different from that of the doped semiconductor layer.
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Citations
19 Claims
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1. An isolation structure, comprising:
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a doped semiconductor layer in a trench in a semiconductor substrate, having the same conductivity type as the substrate; gate dielectric between the doped semiconductor layer and the substrate; and a diffusion region disposed besides a source/drain (S/D) region in the substrate, formed by dopant diffusion through the gate dielectric from the doped semiconductor layer, wherein the diffusion region has a first conductivity type and the source/drain region has a second conductivity type. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A device structure, comprising:
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a semiconductor substrate having a first conductivity type; an isolation structure, including a first doped semiconductor layer having the first conductivity type in a first trench in the substrate, gate dielectric between the first doped semiconductor layer and the substrate, and a diffusion region in the substrate formed by dopant diffusion through the gate dielectric from the first doped semiconductor layer; a first vertical transistor in the substrate at a first side of the isolation structure, including a first source/drain (S/D) region beside the diffusion region and a second source/drain (S/D) region over the first S/D region both having a second conductivity type. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification