Circuits and methods for calibration of a motion detector

• US 8,299,783 B2
• Filed: 08/27/2009
• Issued: 10/30/2012
• Est. Priority Date: 08/27/2009
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Fernandez, Devon, Forrest, Glenn A.
• Primary Examiner(s): Aurora, Reena
• Application Number:
  US12/548,738
• Publication Number:
  US 20110048102A1
• Time in Patent Office: 1,160 Days
• Field of Search: 324/207.25, 324/225, 324/202, 324/207.12
• US Class Current: 324/207.25
• CPC Class Codes: G01D 5/2448 Correction of gain, threshold, offset or phase control

Abstract

A circuit to detect a movement of an object has a calibration time period that ends when peak detectors in the circuit stop updating for a predetermined amount of time. A method associated with the circuit is also described.

Claims

1. A circuit for detecting a movement of an object, comprising:

at least one magnetic field sensing element for generating a DIFF signal proportional to a magnetic field associated with the object;

at least one motion detector coupled to receive the DIFF signal and configured to generate a tracking signal to track the DIFF signal so as to move toward a peak of the DIFF signal, wherein the at least one motion detector comprises;

a positive digital-to-analog converter (PDAC) configured to generate a PDAC output signal to track the DIFF signal during a PDAC update time interval within a calibration time period and to hold the DIFF signal at times outside of the PDAC update time interval within the calibration time period, wherein the calibration time period is a time period during which at least one aspect of the circuit is calibrated, and wherein the PDAC update time interval is a time interval within the calibration time period during which the PDAC is updated;

a negative digital-to-analog converter (NDAC) configured to generate an NDAC output signal to track the DIFF signal during an NDAC update time interval within the calibration time period and to hold the DIFF signal at times outside of the NDAC update time interval within the calibration time period, wherein the NDAC update time interval is a time interval within the calibration time period during which the NDAC is updated; and

an update logic circuit coupled to the PDAC and to the NDAC, wherein the update logic circuit is configured to establish an end of the calibration time period by determining if a first time period since an end of the PDAC update time interval is greater than a first predetermined time threshold and by determining if a second time period since an end of the NDAC update time interval is greater than a second predetermined time threshold.

2. The circuit of claim 1, wherein the first and second predetermined time thresholds are the same predetermined time threshold, and wherein the update logic circuit comprises:

a timer circuit configured to generate a timer circuit output signal configured to change state in response to both the first time period and the second time period being greater than the predetermined time threshold.

3. The circuit of claim 2, wherein the timer circuit comprises:

a counter coupled to receive a clock signal and configured to generate a count output signal;

a DAC coupled to receive the count output signal and configured to generate a DAC output signal; and

a comparator coupled to receive the DAC output signal, coupled to receive a predetermined threshold signal, and configured to generate the timer circuit output signal having a first state indicative of the DAC output signal being less than the predetermined threshold signal and a second different state indicative of the DAC output signal being greater than the predetermined threshold signal.

4. The circuit of claim 2, wherein the timer circuit comprises:

a counter coupled to receive a clock signal, coupled to receive a predetermined preset count signal, and configured to generate the timer circuit output signal having a first state indicative of a pulse count of the clock signal being less than the predetermined preset count signal and a second different state indicative of the pulse count of the clock signal being equal to the predetermined preset count signal.

5. The circuit of claim 2, wherein the update logic circuit further comprises:

an update controller coupled to receive the timer circuit output signal, coupled to receive a first comparison signal indicative of the DIFF signal being above the PDAC output signal, coupled to receive a second comparison signal indicative of the DIFF signal being below the NDAC output signal, and configured to cause the PDAC output signal to track positive-going excursions of the DIFF signal and the NDAC output signal to track negative-going excursions of the DIFF signal in response to states of the timer circuit output signal, the first comparison signal, and the second comparison signal, and configured to cause the PDAC output signal to hold a positive peak signal and the NDAC output signal to hold a negative peak signal in response to other different states of the timer circuit output signal, the first comparison signal, or the second comparison signal.

6. The circuit of claim 1, wherein the at least one magnetic field sensing element comprises at least two magnetic field sensing elements for generating an RDIFF signal and an LDIFF signal, and wherein the at least one motion detector comprises first and second motion detectors, the first motion detector coupled to receive the RDIFF signal and the second motion detector coupled to receive the LDIFF signal.

7. The circuit of claim 6, wherein first motion detector and the second motion detector are configured to generate tracking signals to track the RDIFF signal and the LDIFF signal, respectively, wherein the first motion detector comprises:

a first PDAC configured to generate a first PDAC output signal to track the RDIFF signal during a first PDAC update time interval within a first calibration time period and to hold the RDIFF signal at times outside of the first PDAC update time interval within the first calibration time period;

a first NDAC configured to generate a first NDAC output signal to track the RDIFF signal during a first NDAC update time interval within the first calibration time period and to hold the RDIFF signal at times outside of the first NDAC update time interval within the first calibration time period; and

a first update logic circuit coupled to the first PDAC and to the first NDAC, wherein the first update logic circuit is configured to establish an end of the first calibration time period by determining if a first time period since an end of the first PDAC update time interval is greater than a first predetermined time threshold and by determining if a second time period since an end of the first NDAC update time interval is greater than a second predetermined time threshold, and wherein the second motion detector comprises;

a second PDAC configured to generate a second PDAC output signal to track the LDIFF signal during a second PDAC update time interval within a second calibration time period and to hold the LDIFF signal at times outside of the second PDAC update time interval within the second calibration time period;

a second NDAC configured to generate a second NDAC output signal to track the LDIFF signal during a second NDAC update time interval within the second calibration time period and to hold the LDIFF signal at times outside of the second NDAC update time interval within the second calibration time period; and

a second update logic circuit coupled to the second PDAC and to the second NDAC, wherein the second update logic circuit is configured to establish an end of the second calibration time period by determining if a third time period since an end of the second PDAC update time interval is greater than a third predetermined time threshold and by determining if a fourth time period since an end of the second NDAC update time interval is greater than a fourth predetermined time threshold.

8. The circuit of claim 7, wherein the first and second predetermined time thresholds are the same first calibration time threshold and wherein the third and fourth predetermined time thresholds are the same second calibration time threshold, wherein the first update logic circuit comprises:

a first timer circuit configured to generate a first timer circuit output signal configured to change state in response to both the first time period and the second time period being greater than the first calibration time threshold, and wherein the second update logic circuit comprises;

a second timer circuit configured to generate a second timer circuit output signal configured to change state in response to both the third time period and the fourth time period being greater than the second calibration time threshold.

9. The circuit of claim 8, wherein the first and second timer circuits each comprise:

a respective counter coupled to receive a respective clock signal and configured to generate a respective count output signal;

a respective DAC coupled to receive the respective count output signal and configured to generate a respective DAC output signal; and

a respective comparator coupled to receive the respective DAC output signal, coupled to receive a respective predetermined threshold signal, and configured to generate the first or second timer circuit output signal, respectively, each timer circuit output signal having a first state indicative of the respective DAC output signal being less than the respective predetermined threshold signal and a second different state indicative of the respective DAC output signal being greater than the respective predetermined threshold signal.

10. The circuit of claim 8, wherein the first and second timer circuits each comprise:

a respective counter coupled to receive a respective clock signal, coupled to receive a respective predetermined preset count signal, and configured to generate the first or second timer circuit output signal respectively, each timer circuit output signal having a first state indicative of a pulse count of the respective clock signal being less than the respective predetermined preset count signal and a second different state indicative of the pulse count of the respective clock signal being equal to the respective predetermined preset count signal.

11. The circuit of claim 8, wherein the first update logic circuit further comprises:

a first update controller coupled to receive the first timer circuit output signal, coupled to receive a first comparison signal indicative of the RDIFF signal being above the first PDAC output signal, coupled to receive a second comparison signal indicative of the RDIFF signal being below the first NDAC output signal, and configured to cause the first PDAC output signal to track positive-going excursions of the RDIFF signal and the first NDAC output signal to track negative-going excursions of the RDIFF signal in response to states of the first timer output signal, the first comparison signal, and the second comparison signal, and configured to cause the first PDAC output signal to hold a first positive peak signal and the first NDAC output signal to hold a first negative peak signal in response to other different states of the first timer output signal, the first comparison signal, or the second comparison signal, and wherein the second update logic circuit further comprises;

a second update controller coupled to receive the second timer circuit output signal, coupled to receive a third comparison signal indicative of the LDIFF signal being above the second PDAC output signal, coupled to receive a fourth comparison signal indicative of the LDIFF signal being below the second NDAC output signal, and configured to cause the second PDAC output signal to track positive-going excursions of the LDIFF signal and the second NDAC output signal to track negative-going excursions of the LDIFF signal in response to states of the second timer circuit output signal, the third comparison signal, and the fourth comparison signal, and configured to cause the second PDAC output signal to hold a second positive peak signal and the second NDAC output signal to hold a second positive peak signal in response to other different states of the second timer circuit output signal, the third comparison signal, or the fourth comparison signal.

12. A method, used in a magnetic field sensor, of detecting a movement of an object, comprising:

generating a DIFF signal with at least one magnetic field sensing element, wherein the DIFF signal is proportional to a magnetic field associated with the object;

generating a tracking signal to track the DIFF signal, wherein the generating the tracking signal comprises;

generating a positive digital-to-analog converter (PDAC) output signal to track the DIFF signal during a PDAC update time interval within a calibration time period and to hold the DIFF signal at times outside of the PDAC update time interval within the calibration time period, wherein the calibration time period is a time period during which at least one aspect of the magnetic field sensor is calibrated, and wherein the update time interval is a time interval within the calibration time period during which the PDAC is updated;

generating a negative digital-to-analog converter (NDAC) output signal to track the DIFF signal during an NDAC update time interval within the calibration time period and to hold the DIFF signal at times outside of the NDAC update time interval within the calibration time period, wherein the NDAC update time interval is a time interval within the calibration time period during which the NDAC is updated; and

establishing an end of the calibration time period, wherein the establishing comprises;

determining if a first time period since an end of the PDAC update time interval is greater than a first predetermined time threshold; and

determining if a second time period since an end of the NDAC update time interval is greater than a second predetermined time threshold.

13. The method of claim 12, wherein the first and second predetermined time thresholds are the same predetermined time threshold, and wherein the establishing comprises:

generating a timer circuit output signal configured to change state in response to both the first time period and the second time period being greater than the predetermined time threshold.

14. The method of claim 13, wherein the generating the timer circuit output signal comprises:

generating a count output signal;

generating a DAC output signal in response to the count output signal; and

generating, in response to the DAC output signal, the timer circuit output signal having a first state indicative of the DAC output signal being less than a predetermined threshold signal and a second different state indicative of the DAC output signal being greater than the predetermined threshold signal.

15. The method of claim 13, wherein the generating the timer circuit output signal comprises:

predetermining a preset count signal;

generating a clock signal; and

generating, in response to the predetermined preset count signal, the timer circuit output signal having a first state indicative of a pulse count of the clock signal being less than the predetermined preset count signal and a second different state indicative of the pulse count of the clock signal being equal to the predetermined preset count signal.

16. The method of claim 13, wherein the establishing further comprises:

generating a first comparison signal indicative of the DIFF signal being above the PDAC output signal;

generating a second comparison signal indicative of the DIFF signal being below the NDAC output signal;

causing the PDAC output signal to track positive-going excursions of the DIFF signal and the NDAC output signal to track negative-going excursions of the DIFF signal in response to states of the timer circuit output signal, the first comparison signal, and the second comparison signal; and

causing the PDAC output signal to hold a positive peak signal and the NDAC output signal to hold a negative peak signal in response to other different states of the timer circuit output signal, the first comparison signal, or the second comparison signal.

17. The method of claim 12, wherein the at least one magnetic field sensing element comprises at least two magnetic field sensing elements for generating an RDIFF signal and an LDIFF signal, and wherein the generating the tracking signal comprises generating first and second tracking signals, respectively.

18. The method of claim 17, wherein the generating the first tracking signal comprises:

generating a first PDAC output signal to track the RDIFF signal during a first PDAC update time interval within a first calibration time period and to hold the RDIFF signal at times outside of the first PDAC update time interval within the first calibration time period;

generating a first NDAC output signal to track the RDIFF signal during a first NDAC update time interval within the first calibration time period, wherein, after the first calibration time period and to hold the RDIFF signal at times outside of the first NDAC update time interval within the first calibration time period; and

establishing an end of the first calibration time period, wherein the establishing comprises;

determining if a first time period since an end of the first PDAC update time interval is greater than a first predetermined time threshold; and

determining if a second time period since an end of the first NDAC update time interval is greater than a second predetermined time threshold, and

wherein the generating the second tracking signal comprises;

generating a second PDAC output signal to track the LDIFF signal during a second PDAC update time interval within a second calibration time period and to hold the LDIFF signal at times outside of the second PDAC update time interval within the second calibration time period;

generating a second NDAC output signal to track the LDIFF signal during a second NDAC update time interval within the second calibration time period, wherein, after the second calibration time period and to hold the LDIFF signal at times outside of the second NDAC update time interval within the second calibration time period; and

establishing an end of the second calibration time period, wherein the establishing comprises;

determining if a third time period since an end of the second PDAC update time interval is greater than a third predetermined time threshold; and

determining if a fourth time period since an end of the second NDAC update time interval is greater than a fourth predetermined time threshold.

19. The method of claim 18, wherein the first and second predetermined time thresholds are the same first calibration time threshold and wherein the third and fourth predetermined time thresholds are the same second calibration time threshold, wherein the establishing the first calibration time period comprises:

generating a first timer circuit output signal configured to change state in response to both the first time period and the second time period being greater than the first calibration time threshold, and wherein the establishing the second calibration time period comprises;

generating a second timer circuit output signal configured to change state in response to both the third time period and the fourth time period being greater than the second calibration time threshold.

20. The method of claim 19, wherein the generating the first timer circuit output signal and the generating the second timer circuit output signal each comprise:

generating a respective count output signal;

generating a respective DAC output signal in response to the respective count output signal; and

generating the first or second timer circuit output signal, respectively, each timer circuit output signal having a first state indicative of the respective DAC output signal being less than a respective predetermined threshold signal and a second different state indicative of the respective DAC output signal being greater than the respective predetermined threshold signal.

21. The method of claim 19, wherein the generating the first timer circuit output signal and the generating the second timer circuit output signal each comprise:

predetermining a respective preset count signal; and

generating, in response to the respective preset count signal, the first or second timer circuit output signals, respectively, having a first state indicative of a pulse count of a respective clock signal being less than the respective predetermined preset count signal and a second different state indicative of the pulse count of the respective clock signal being equal to the respective predetermined preset count signal.

22. The method of claim 19, wherein the establishing the first calibration time period comprises:

receiving a first comparison signal indicative of the RDIFF signal being above the first PDAC output signal;

receiving a second comparison signal indicative of the RDIFF signal being below the first NDAC output signal;

causing the first PDAC output signal to track positive-going excursions of the RDIFF signal and the first NDAC output signal to track negative-going excursions of the RDIFF signal in response to states of the first timer output signal, the first comparison signal, and the second comparison signal; and

causing the first PDAC output signal to hold a first positive peak signal and the first NDAC output signal to hold a first negative peak signal in response to other different states of the first timer output signal, the first comparison signal, or the second comparison signal, and wherein the establishing the second calibration time period comprises;

receiving a third comparison signal indicative of the LDIFF signal being above the second PDAC output signal;

receiving a fourth comparison signal indicative of the LDIFF signal being below the second NDAC output signal;

causing the second PDAC output signal to track positive-going excursions of the LDIFF signal and the second NDAC output signal to track negative-going excursions of the LDIFF signal in response to states of the second timer circuit output signal, the third comparison signal, and the fourth comparison signal; and

causing the second PDAC output signal to hold a second positive peak signal and the second NDAC output signal to hold a second negative peak signal in response to other different states of the second timer circuit output signal, the third comparison signal, or the fourth comparison signal.

23. A method, used in a magnetic field sensor, of detecting movement of an object, comprising:

generating a magnetic field signal with at least one magnetic field sensing element, wherein the magnetic field signal is proportional to a magnetic field associated with the object;

generating a tracking signal during a calibration mode of operation that moves toward a peak of the magnetic field signal at least until the peak is reached, wherein the calibration mode occurs during a calibration time period during which at least one as aspect of the magnetic field sensor is calibrated; and

terminating the calibration mode of operation after a predetermined time interval has lapsed since the tracking signal reached the peak of the magnetic field signal.

24. The method of claim 23, wherein terminating comprises:

generating, with a first DAC, a first DAC output signal configured to track the magnetic field signal during a first DAC update time interval;

generating, with a second DAC, a second DAC output signal configured to track the magnetic field signal during a second DAC update time interval;

determining if a first time period since an end of the first DAC update time interval is greater than a first predetermined time threshold;

determining if a second time period since an end of the second DAC update time interval is greater than a second predetermined time threshold; and

terminating the calibration mode of operation after a predetermined time interval has lapsed since the end of the first DAC update time interval or since an end of the second DAC update time interval.

25. The method of claim 24, wherein the first DAC is configured to hold positive peaks of the magnetic field signal and wherein the second DAC is configured to hold negative peaks of the magnetic field signal.