ELUT: enhanced look-up table signal processing

• US 8,300,058 B2
• Filed: 03/10/2008
• Issued: 10/30/2012
• Est. Priority Date: 03/10/2008
• Status: Active Grant

• Current Assignee: MobilEye Vision Technologies Ltd. (Intel Corporation)
• Original Assignee: Mobileye Technologies Limited (Intel Corporation)
• Inventors: Kreinin, Yossi, Sixou, Emmanuel, Sajman, Roman, Navon, Mois P.
• Primary Examiner(s): Crawford, Jacinta M
• Application Number:
  US12/045,033
• Publication Number:
  US 20090228737A1
• Time in Patent Office: 1,695 Days
• Field of Search: 345/519, 345/559, 345/530
• US Class Current: 345/559
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30098 Register arrangements

Abstract

An electronic device including an array of addressable registers storing data. An input register connected to the array stores an input command parameter (e.g an opcode of a command) and its associated operands in one or more input registers connected to the addressable register array. A single instance of a command accesses the at least one register of the array. Based on the input command parameter, the command for all of the address operands: reads a datum of the data previously stored in at least one register, updates the datum thereby producing an updated datum, and writes the updated datum into at least one register. The command has multiple address operands referencing the one or more registers and supports two or more of the address operands being identical. The device includes logic circuitry which provides a logical output signal to the processing circuitry indicating which, if any, of the address operands are identical. The processing circuitry based on the logical output, processes first any identical address operands prior to writing the updated datum into the at least one register so that a new instance of the command begins processing by the processing circuitry on a consecutive clock pulse and the command throughput is one command per clock pulse.

Claims

1. An electronic device implemented on a semiconductor chip, the electronic device, comprising:

(a) an array of addressable registers storing a plurality of data;

(b) a plurality of input registers operatively connected to said array of addressable registers, wherein said input registers are configured to store an input command parameter and a plurality of operands;

wherein said operands include a plurality of address operands referencing at least one register of said array of addressable registers;

(c) processing circuitry configured to process, based on said input command parameter, said data;

wherein a single instance of a command accesses said at least one register of said array of addressable registers, and based on said input command parameter said processing circuitry for all of said address operands;

reads a datum of said data previously stored in said at least one register, updates said datum thereby producing an updated datum, and writes said updated datum into said at least one register;

(d) logic circuitry operatively attached between said input registers and said processing circuitry, said logic circuitry configured to provide a logical output signal to said processing circuitry indicating which if any of said address operands are identical thereby supporting at least two of said address operands being identical.

2. The electronic device, according to claim 1, wherein said processing circuitry based on said logical output signal, is configured to process any said identical address operands prior to writing said updated datum into said at least one register.

3. The electronic device, according to claim 1, further comprising:

(e) a clock adapted to provide a plurality of clock pulses, wherein said processing circuitry processes said command during at least three clock pulses, wherein a new instance of said command begins processing by said processing circuitry on a consecutive clock pulse so that there is a command throughput of at least one command per clock pulse.

4. The electronic device, according to claim 1, wherein said command sets a bin of a histogram by an incremental value.

5. The electronic device, according to claim 1, wherein said command increments a bin of a histogram by an incremental value.

6. The electronic device, according to claim 1, wherein said command compares said datum with at least one incremental value, said command calculates the minimal value selected from the group of said datum and said at least one incremental value and said command writes said minimal value as said updated datum.

7. The electronic device, according to claim 1, wherein said command compares said datum with at least one incremental value, wherein said command calculates the maximal value selected from the group of said datum and said at least one incremental value and writes said maximal value as updated datum.

8. The electronic device, according to claim 1, further comprising:

(e) a second array of registers operatively connected to said array of addressable registers;

wherein said registers of said second array store a plurality of locations referencing a portion of said array of addressable registers.

9. The electronic device, according to claim 8, wherein said portion is contiguous, the electronic device further comprising:

(f) an input control register operatively connected to said logic circuitry;

wherein the size of said contiguous portion is specified by a size value stored in said input control register.

10. The electronic device, according to claim 9, wherein said command accesses a location solely within said contiguous portion of said array of addressable registers.

11. The electronic device, according to claim 8, further comprising

(f) an input control register operatively connected to said logic circuitry, wherein a door-knock value is stored in said input control register, wherein upon initiating said command, said door-knock value is decremented and only upon said door-knock value equaling a previously defined minimum value is said updated datum written into said at least one register.

12. An electronic device implemented on a semiconductor chip, the electronic device, comprising:

(a) a first array of addressable registers;

(b) a plurality of input registers operatively connected to said first array;

wherein said input registers are adapted to store an input command parameter, a plurality of operands, and a size value; and

(c) a second array of registers operatively connected to said first array;

wherein said operands reference said second array of registers;

wherein said registers of said second array are adapted to store a plurality of address operands referencing a plurality of locations of said first array and wherein the accessible area of said addressable registers is specified by said size value.

13. The electronic device, according to claim 12, wherein said address operands as stored respectively in said second array are calculated based on said input command parameter modulo said size value.

14. The electronic device, according to claim 12, further comprising:

(d) processing circuitry which upon processing a single instance of a command, based on said input command parameter, processes a plurality of data stored in said locations.

15. The electronic device, according to claim 14, wherein a single instance of said command accesses at least one of said addressable registers of said first array of said accessible area, and based on said input command parameter, said command for said at least one addressable register and for all said address operands:

reads a datum of said data previously stored in said at least one addressable register of said first array of addressable registers, updates said datum thereby producing an updated datum, and writes said updated datum into said at least one addressable register of said first array of addressable registers.

16. The electronic device, according to claim 15, wherein the single instance of the command referencing the at least one addressable register of the array of addressable registers supports at least two of said address operands being identical.

17. The electronic device, according to claim 15, further comprising:

(e) a clock adapted to provide a plurality of clock pulses, wherein said processing circuitry is adapted to process said command during at least three clock pulses, wherein a new instance of said command begins processing by said processing circuitry on consecutive clock pulses so that there is a command throughput of one command per clock pulse.

18. An electronic device implemented on a semiconductor chip, the electronic device comprising:

(a) an array of addressable registers;

(b) a plurality of input registers operatively connected to said array of addressable registers, said input registers adapted to store an input command parameter and a plurality of operands;

wherein said operands include a plurality of address operands referencing at least one addressable register of said array of addressable registers;

wherein said input command parameter specifies a command;

wherein a single instance of said command accesses the at least one addressable register of the array;

(c) processing circuitry which executes the command thereby accessing for all said address operands at least one of said addressable registers of said array, and based on said input command parameter writes a datum into said at least one register; and

(d) a clock operatively attached to said processing circuitry provides a plurality of clock pulses, wherein the command throughput in number of commands processed per clock pulse is independent of the number of said address operands.

19. The electronic device, according to claim 18, wherein said command throughput is one command per clock pulse.

20. The electronic device, according to claim 18, further comprising the step of

(e) an input control register operatively connected to said processing circuitry, wherein a door-knock value is stored in said input control register, and upon receiving said command, said door-knock value is decremented and only upon said door-knock value equaling a previously defined minimum value is said datum written into said at least one addressable register of said array of addressable registers.