Liquid crystal display and thin film transistor array panel usable with the liquid crystal display

• US 8,300,192 B2
• Filed: 11/11/2010
• Issued: 10/30/2012
• Est. Priority Date: 10/06/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Jang-Kun
• Primary Examiner(s): CHIEN, LUCY P
• Application Number:
  US12/944,617
• Publication Number:
  US 20110114958A1
• Time in Patent Office: 719 Days
• Field of Search: None
• US Class Current: 349/141
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel

Abstract

A liquid crystal display with improved viewing angle and uncompromised transmittance is provided, along with a thin film transistor (TFT) array panel usable for such liquid crystal display. The TFT array panel includes a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines formed on the substrate and intersecting the gate lines, and a plurality of thin film transistors. Each of the thin film transistors includes a gate electrode connected to one of the gate lines, a source electrode connected to one of the data lines, and a drain electrode. The TFT array panel also includes a plurality of pixel electrodes, each of the pixel electrodes connected to one of the drain electrodes and having a pair of oblique edges parallel to each other, and covering at least a portion of the drain electrodes.

Claims

1. A thin film transistor array panel comprising:

a substrate;

a gate line disposed on the substrate;

a first data line disposed on the substrate and intersecting the gate line;

a gate insulating layer disposed between the gate line and the first data line;

a thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the first data line, and a drain electrode;

a plurality of color filters disposed on the thin film transistor and the gate insulating layer;

a passivation layer disposed on the color filters; and

a first pixel electrode disposed on the passivation layer, connected to the drain electrode, and having a first edge and a second edge facing the first edge, wherein the first and second edges each have portions oriented at one or more acute angles with respect to the gate line,

wherein the first data line comprises a first crossing portion crossing from the first edge to the second edge at a first location along the first pixel electrode, the first data line also comprising a second crossing portion crossing from the first edge to the second edge at a second location along the first pixel electrode;

wherein the second location is different from the first location; and

wherein the first crossing portion and the second crossing portion are oriented at different angles with respect to the gate line.

2. The thin film transistor array panel of claim 1, wherein the first pixel electrode has a generally chevron shape.

3. The thin film transistor array panel of claim 2, further comprising a second pixel electrode disposed adjacent to the first pixel electrode,

wherein the first data line overlaps the first and the second pixel electrodes.

4. The thin film transistor array panel of claim 2, wherein the first data lines further comprise a perpendicular portion that is generally perpendicular to the gate line.

5. The thin film transistor array panel of claim 4, wherein the first and second crossing portions each cross at least one of the first edge and the second edge at generally right angles, and

wherein the perpendicular portion is disposed between the first crossing portion and the second crossing portion.