Two terminal programmable hot channel electron non-volatile memory
First Claim
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1. A two terminal programmable non-volatile device situated on a substrate, the device comprising:
- a first diffusion region coupled to a first terminal; and
a second diffusion region coupled to a second terminal; and
a channel coupling said first diffusion region and second diffusion region;
a floating gate comprised of polysilicon, which floating gate is situated over at least a portion of said channel;
wherein the device is adapted such that a channel hot electron current can be induced in said channel by a voltage potential imposed across said first terminal and said second terminal by a single program voltage, and which voltage potential is sufficient to cause injection into said floating gate and program the device,wherein the first diffusion region overlaps a sufficient areal portion of said floating gate to permit a threshold voltage of the device to be controlled by a coupling ratio determined by said areal portion and said single program voltage applied to said second diffusion region.
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Abstract
A programmable two terminal non-volatile device uses a floating gate that can be programed by a hot electron injection induced by a potential between a source and drain. The floating gate layer can also function as a FET gate for other circuits in an integrated circuit containing an array of the devices. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.
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Citations
23 Claims
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1. A two terminal programmable non-volatile device situated on a substrate, the device comprising:
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a first diffusion region coupled to a first terminal; and a second diffusion region coupled to a second terminal; and a channel coupling said first diffusion region and second diffusion region; a floating gate comprised of polysilicon, which floating gate is situated over at least a portion of said channel; wherein the device is adapted such that a channel hot electron current can be induced in said channel by a voltage potential imposed across said first terminal and said second terminal by a single program voltage, and which voltage potential is sufficient to cause injection into said floating gate and program the device, wherein the first diffusion region overlaps a sufficient areal portion of said floating gate to permit a threshold voltage of the device to be controlled by a coupling ratio determined by said areal portion and said single program voltage applied to said second diffusion region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A two terminal programmable non-volatile device situated on a substrate, the device comprising:
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a first n-type diffusion region coupled to a first terminal; and a second n-type diffusion region coupled to a second terminal; and an n-type channel coupling said first diffusion region and second diffusion region; a floating gate comprised of polysilicon, which floating gate is situated over at least a portion of said channel and is adapted to store electrical charge corresponding to a logic state of the device; further wherein the device is adapted such that a channel hot electron current can be induced in said channel sufficient to cause injection into said floating gate using a single programming voltage applied only to at most one of said first and second terminals, wherein the first diffusion region overlaps a sufficient areal portion of said floating gate to permit a threshold voltage of the device to be controlled by a coupling ratio determined by said areal portion and said single programming voltage applied to said second diffusion region.
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15. A one-time programmable (OTP) two terminal memory device incorporated on a silicon substrate with at least one other additional logic device or non-OTP memory device, characterized in that:
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a. the OTP memory device has a first diffusion region and a second diffusion region; b. the OTP memory device has a floating gate overlying at least in part a channel region extending between said first diffusion region and said second diffusion region; wherein said channel is adapted to have a low resistance when the device is in an unprogrammed state, and a high resistance when the device is in a programmed state; and c. any and all regions and structures of said OTP memory device are derived solely from corresponding regions and structures used as components of the at least one device, including said n-type diffusion region which is used by said at least one device; d. the OTP memory device can be set to said programmed state by hot channel electron injection induced by a potential between said first diffusion region and said second diffusion region caused by a single programming voltage coupled to the OTP memory device. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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Specification