Two terminal programmable hot channel electron non-volatile memory

• US 8,300,470 B2
• Filed: 04/04/2011
• Issued: 10/30/2012
• Est. Priority Date: 11/01/2007
• Status: Expired due to Fees

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Liu, David K.Y.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US13/079,486
• Publication Number:
  US 20110176365A1
• Time in Patent Office: 575 Days
• Field of Search: 365/185.18, 365/185.24
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A programmable two terminal non-volatile device uses a floating gate that can be programed by a hot electron injection induced by a potential between a source and drain. The floating gate layer can also function as a FET gate for other circuits in an integrated circuit containing an array of the devices. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A two terminal programmable non-volatile device situated on a substrate, the device comprising:

a first diffusion region coupled to a first terminal; and

a second diffusion region coupled to a second terminal; and

a channel coupling said first diffusion region and second diffusion region;

a floating gate comprised of polysilicon, which floating gate is situated over at least a portion of said channel;

wherein the device is adapted such that a channel hot electron current can be induced in said channel by a voltage potential imposed across said first terminal and said second terminal by a single program voltage, and which voltage potential is sufficient to cause injection into said floating gate and program the device,

wherein the first diffusion region overlaps a sufficient areal portion of said floating gate to permit a threshold voltage of the device to be controlled by a coupling ratio determined by said areal portion and said single program voltage applied to said second diffusion region.

2. The programmable device of claim 1 wherein said single program voltage can be applied across said first terminal and said second terminal.

3. The programmable device of claim 1 wherein a substrate under said channel can be biased to enhance hot electron generation.

4. The programmable device of claim 1 wherein charge can be imparted to said floating gate by the single program voltage through areal capacitive coupling between said floating gate and said first diffusion region.

5. The programmable device of claim 1 wherein said device can be re-programmed.

6. The programmable device of claim 1 wherein a state of said floating gate can be determined by a read signal applied to said second diffusion region.

7. The programmable device of claim 6, wherein said read signal is less than about 1 volt.

8. The programmable device of claim 1 wherein said device is part of a programmable array embedded with at least one of a separate logic circuit and/or a memory circuit in an integrated circuit.

9. The programmable device of claim 1 wherein said device is part of a programmable array embedded with separate analog circuits within an integrated circuit.

10. The programmable device of claim 1 wherein said floating gate is comprised of a polysilicon layer used for a logic gate within the same integrated circuit.

11. The programmable device of claim 1 wherein said device is associated with at least one of a data encryption circuit;

a reference trimming circuit;

a manufacturing ID;

or a security ID.

12. The programmable device of claim 1, wherein a threshold voltage of said device can be set to multiple discrete levels.

13. The programmable device of claim 1, wherein the device is part of a programmable memory array.

14. A two terminal programmable non-volatile device situated on a substrate, the device comprising:

a first n-type diffusion region coupled to a first terminal; and

a second n-type diffusion region coupled to a second terminal; and

an n-type channel coupling said first diffusion region and second diffusion region;

a floating gate comprised of polysilicon, which floating gate is situated over at least a portion of said channel and is adapted to store electrical charge corresponding to a logic state of the device;

further wherein the device is adapted such that a channel hot electron current can be induced in said channel sufficient to cause injection into said floating gate using a single programming voltage applied only to at most one of said first and second terminals,

wherein the first diffusion region overlaps a sufficient areal portion of said floating gate to permit a threshold voltage of the device to be controlled by a coupling ratio determined by said areal portion and said single programming voltage applied to said second diffusion region.

15. A one-time programmable (OTP) two terminal memory device incorporated on a silicon substrate with at least one other additional logic device or non-OTP memory device, characterized in that:

a. the OTP memory device has a first diffusion region and a second diffusion region;

b. the OTP memory device has a floating gate overlying at least in part a channel region extending between said first diffusion region and said second diffusion region;

wherein said channel is adapted to have a low resistance when the device is in an unprogrammed state, and a high resistance when the device is in a programmed state; and

c. any and all regions and structures of said OTP memory device are derived solely from corresponding regions and structures used as components of the at least one device, including said n-type diffusion region which is used by said at least one device;

d. the OTP memory device can be set to said programmed state by hot channel electron injection induced by a potential between said first diffusion region and said second diffusion region caused by a single programming voltage coupled to the OTP memory device.

16. The OTP memory device of claim 15 wherein said single programming voltage results in a programming voltage being coupled through an areal portion between said first diffusion region and said floating gate.

17. The OTP memory device of claim 15 wherein a coupling ratio in said areal portion is at least 90%.

18. The OTP memory device of claim 15 wherein said floating gate can be erased.

19. The OTP memory device of claim 15 wherein said device can be re-programmed.

20. The OTP memory device of claim 15 wherein said floating gate is eraseable by an erase voltage applied to a source region.

21. The OTP memory device of claim 15 wherein a state of said floating gate can be determined by a read signal applied to said first diffusion region.

22. The OTP memory device of claim 15 wherein said device is associated with at least one of a data encryption circuit;

a reference trimming circuit;

a manufacturing ID;

or a security ID.

23. The OTP memory device of claim 15, wherein a threshold voltage of said OTP memory device can be set to multiple discrete levels.