System and transceiver clocking to minimize required number of reference sources in multi-function cellular applications including GPS

• US 8,301,098 B2
• Filed: 06/23/2010
• Issued: 10/30/2012
• Est. Priority Date: 06/24/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Uehara, Gregory, Zaslavsky, Alexander, Brunn, Brian
• Primary Examiner(s): Tran, Tuan A
• Application Number:
  US12/821,595
• Publication Number:
  US 20100330931A1
• Time in Patent Office: 860 Days
• Field of Search: 455255-265, 4551921-1923, 342 98-103, 342/199, 342/357.62, 342/357.64, 342/357.75, 331/18, 331/34, 331/60
• US Class Current: 455/260
• CPC Class Codes: G01S 19/23 Testing, monitoring, correcting or calibrating of receiver elements
• CPC Class Codes: H03J 1/005 in a loop
• CPC Class Codes: H03J 7/02 Automatic frequency control H03J7/18 takes precedence
• CPC Class Codes: H03J 7/04 where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/22 using more than one loop
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/3805 with built-in auxiliary receivers
• CPC Class Codes: H04W 84/12 WLAN [Wireless Local Area Networks]

Abstract

A system comprises a first clock module configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). A global position system (GPS) module is configured to receive the first clock reference. An integrated circuit for a cellular transceiver includes a system phase lock loop configured to receive the first clock reference, to perform AFC, and to generate a second clock reference that is AFC corrected.

Claims

1. A system comprising:

a first clock module configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC);

a global positioning system (GPS) module configured to operate in response to the first clock reference;

an integrated circuit for a cellular transceiver, wherein the integrated circuit comprises a system phase lock loop (PLL) configured to (i) operate in response to the first clock reference and (ii) generate a second clock reference by performing AFC on the first clock reference in response to an AFC signal;

a selection module configured to output a selected reference based alternatively on the first clock reference and the second clock reference; and

a baseband module configured to (i) receive the selected reference and (ii) generate the AFC signal.

2. The system of claim 1, wherein the integrated circuit further comprises:

a receiver module configured to receive analog radio frequency (RF) signals and to output digital baseband signals in response to the analog RF signals, wherein the receiver module comprises at least one of

a receiver digital signal processor (DSP) configured to operate in response to a receiver clock reference; and

an analog to digital converter (ADC) configured to operate in response to the receiver clock reference; and

a transmitter module configured to receive digital baseband signals and to output analog transmit RF signals in response to the digital baseband signals, wherein the transmitter module comprises at least one of

a transmitter DSP configured to operate in response to a transmitter clock reference; and

a digital to analog converter (DAC) configured to operate in response to the transmitter clock reference.

3. The system of claim 2, wherein:

the receiver clock reference is a first integer multiple of the second clock reference, the first integer being greater than or equal to one; and

the transmitter clock reference is a second integer multiple of the second clock reference, the second integer being greater than or equal to one.

4. The system of claim 1, wherein the integrated circuit is configured to (i) receive the first clock reference from the first clock module and (ii) output the first clock reference to the GPS module.

5. The system of claim 1, wherein the integrated circuit further comprises:

a receiver PLL module configured to (i) receive the first clock reference and (ii) generate a third clock reference in response to the first clock reference, and

a transmitter PLL module configured to (i) receive the first clock reference and (ii) generate a fourth clock reference in response to the first clock reference.

6. The system of claim 5, wherein the integrated circuit further comprises:

a downconverter configured to generate analog baseband signals in response to received analog radio frequency (RF) signals and the third clock reference, and

an upconverter configured to generate analog RF signals for transmission in response to the fourth clock reference.

7. The system of claim 1, wherein the integrated circuit comprises:

a receiver PLL module configured to (i) receive the second clock reference and (ii) generate a third clock reference in response to the second clock reference, and

a transmitter PLL module configured to (i) receive the second clock reference and (ii) generate a fourth clock reference in response, to the second clock reference.

8. The system of claim 7, wherein the integrated circuit further comprises:

a downconverter configured to generate analog baseband signals in response to received analog radio frequency (RF) signals and the third clock reference, and

an upconverter configured to generate analog RF signals for transmission in response to the fourth clock reference.

9. The system of claim 1, further comprising a second integrated circuit comprising the baseband module.

10. The system of claim 1, further comprising at least one of:

a WiFi module configured to receive the first clock reference from the integrated circuit, and

a Bluetooth module configured to receive the first clock reference from the integrated circuit.

11. The system of claim 1, wherein the system PLL includes:

a phase frequency detector configured to determine a difference between the first clock reference and a third clock reference;

a charge pump configured to receive an output of the phase frequency detector;

a filter configured to filter an output of the charge pump;

a voltage controlled oscillator configured to generate the second clock reference;

a divider configured to (i) receive the second clock reference and (ii) output the third clock reference based on a divisor; and

a fractional adjusting module configured to adjust a ratio of the divisor between two or more integer values during successive intervals.

12. The system of claim 11, wherein the voltage controlled oscillator comprises one of a ring oscillator, a relaxation oscillator, and an LC oscillator.

13. The system of claim 1, wherein the first clock module comprises a temperature controlled crystal oscillator.

14. A method comprising:

generating a first clock reference that is not corrected using automatic frequency correction (AFC);

receiving the first clock reference at a global positioning system (GPS) module;

operating the GPS module in response to the first clock reference;

receiving the first clock reference at an integrated circuit for a cellular transceiver;

generating a second clock reference by performing AFC on the first clock reference using a phase lock loop (PLL) of the integrated circuit in response to an AFC signal;

alternatively selecting one of the first clock reference and the second clock reference as a selected reference;

providing the selected reference to a baseband module; and

generating the AFC signal using the baseband module.

15. The method of claim 14, further comprising:

generating a third clock reference in response to the first clock reference using a receiver PLL; and

generating a fourth clock reference in response to the first clock reference using a transmitter PLL.

16. The method of claim 15, further comprising:

downconverting received analog radio frequency (RF) signals into analog baseband signals in response to the third clock reference; and

upconverting baseband signals for transmission into analog RF signals for transmission in response to the fourth clock reference.

17. The method of claim 14, further comprising:

generating a third clock reference in response to the second clock reference using a receiver PLL; and

generating a fourth clock reference in response to the second clock reference using a transmitter PLL.

18. The method of claim 17, further comprising:

downconverting received analog radio frequency (RF) signals into analog baseband signals in response to the third clock reference; and

upconverting baseband signals for transmission into analog RF signals for transmission in response to the fourth clock reference.

19. The method of claim 14, further comprising selectively outputting one of the first clock reference and the second clock reference from the integrated circuit to the baseband module.

20. The method of claim 14, further comprising buffering and controlling a slew rate of the first clock reference provided to the GPS module.