Specialized processing block for programmable logic device

• US 8,301,681 B1
• Filed: 06/05/2006
• Issued: 10/30/2012
• Est. Priority Date: 02/09/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lee, Kwan Yee Martin, Langhammer, Martin, Nguyen, Triet M., Lin, Yi-Wen
• Primary Examiner(s): Ngo, Chuong D
• Assistant Examiner(s): SANDIFER, MATTHEW D
• Application Number:
  US11/447,474
• Time in Patent Office: 2,339 Days
• Field of Search: 708620-656
• US Class Current: 708/523
• CPC Class Codes: G06F 2207/3884 Pipelining
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/4876 Multiplying
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: H03K 19/17732 Macroblocks

Abstract

A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for performing floating point operations. The floating point circuitry preferably includes rounding and normalization circuitry. To perform mantissa multiplications, the floating point circuitry preferably relies on the aforementioned multipliers of the specialized processing block.

Claims

1. A specialized processing block for a programmable logic device, said specialized processing block comprising:

arithmetic circuitry programmable to provide products of inputs and sums of said products to output a result, said arithmetic circuitry comprising a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators having a respective pair of inputs different from inputs of each other one of said partial product generators and providing a respective plurality of vectors representing a respective partial product,

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product, and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products;

said arithmetic circuitry further comprising;

floating point circuitry that separately processes sign, exponent and mantissa for carrying out floating point operations, and

combined rounding and normalization circuitry for processing said mantissa and said exponent; and

special case control circuitry that controls output of said floating point circuitry;

wherein;

said special case control circuitry comprises;

multiplexer circuitry having inputs representative of said processed sign, said processed exponent, said processed mantissa, and output of said rounding and normalization circuitry; and

circuitry that examines input sign, exponent and mantissa for special cases and controls said multiplexer to output one of (a) an output of said floating point circuitry and (b) a special case output.

2. A programmable logic device comprising the specialized processing block of claim 1.

3. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 2 coupled to the processing circuitry and the memory.

4. A printed circuit board on which is mounted a programmable logic device as defined in claim 2.

5. The printed circuit board defined in claim 4 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

6. The printed circuit board defined in claim 5 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

7. An integrated circuit device comprising the specialized processing block of claim 1.

8. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

an integrated circuit device as defined in claim 7 coupled to the processing circuitry and the memory.

9. A printed circuit board on which is mounted an integrated circuit device as defined in claim 7.

10. The printed circuit board defined in claim 9 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

11. The printed circuit board defined in claim 10 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.