Adaptive mode switching of flash memory address mapping based on host usage characteristics

• US 8,301,826 B2
• Filed: 10/30/2009
• Issued: 10/30/2012
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Gonzalez, Carlos J., Sompel, Mark, Conley, Kevin M.
• Primary Examiner(s): Thai, Tuan
• Assistant Examiner(s): LI, ZHUO H
• Application Number:
  US12/609,789
• Publication Number:
  US 20100049908A1
• Time in Patent Office: 1,096 Days
• Field of Search: 711102-103, 711/5, 711/100, 711/150, 711/200, 711202-203, 36523001-23003
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.

Claims

1. A non-volatile memory system, comprising:

an array of non-volatile memory cells arranged in blocks as a unit of erase, pages therein as a unit of data programming and reading, and planes of a plurality of blocks that are independently accessible;

a controller for operating the array on logically formed metablocks that individually include blocks from a plurality of the planes;

said controller performing operations that include;

responsive to individual write commands from a host with a varying number of units of data and logical addresses of the individual units of data,

determining from the write commands whether (1) a given one or more units of data having consecutive logical addresses are being received or (2) more than said given number of one or more units of data having consecutive logical addresses are being received, and

writing all the data received with individual write commands by (1), in response to determining that the given one or more units of data having consecutive logical addresses are being received, writing the given one or more units of data into at least one page within at least one of the blocks of only one of the planes, and (2), in response to determining that more than said given number of one or more units of data having consecutive logical addresses are being received, writing the more than said given number of units of data in parallel into pages within two or more blocks of one of the metablocks in two or more planes.

2. The non-volatile memory of claim 1, wherein the operations additionally comprises writing an indication into non-volatile memory cells at the same time as the received data that identifies the blocks into which the data are being written in parallel.

3. The non-volatile memory of claim 1, wherein said array of non-volatile memory cells are of the NAND type.

4. The non-volatile memory of claim 1, wherein said array of non-volatile memory operates as multi-state memory.

5. The non-volatile memory of claim 4, wherein selected portions of said array of non-volatile memory operates as binary memory.

6. A memory system, comprising:

a plurality of non-volatile memory cells arranged in a plurality of blocks of memory cells as a unit of erase that are provided in a plurality of independently accessible sub-arrays and multiple pages within individual blocks as units of data programming and reading;

a controller for operating the array on logically formed metablocks that individually include blocks from a plurality of the sub-arrays;

said controller performing operations that include;

sequentially receiving individual write commands with a number of sectors of data to be written into either a single page or into a plurality of pages,

in response to receiving the write commands with a number of sectors of data for a plurality of pages, writing all the received data in parallel into pages within a plurality of blocks of at least one of the metablocks in a plurality of the sub-arrays,

in response to receiving the write commands with a number of one or more sectors of data for only a single page of data, writing all the received data in parallel into individual pages of individual blocks of only one of the sub-arrays, and

maintaining indications in the non-volatile memory cells that are associated with the written sectors of data when the individual sectors have been written into pages within a plurality of blocks of at least one of the metablocks in a plurality of the sub-arrays, and when the individual sectors have been written into individual pages of individual blocks of only one of the sub-arrays.

7. The memory system of claim 6, wherein a file allocation table (FAT) is stored within the non-volatile memory cells and the sectors of data for a single page of data include data of the FAT.

8. The memory system of claim 6, wherein the operations additionally comprises storing the indications with their respective sectors of data as part of headers thereto.

9. The non-volatile memory of claim 6, wherein the operations additionally comprises writing an indication into non-volatile memory cells at the same time as the received data that identifies the blocks into which the data are being written in parallel.

10. The non-volatile memory of claim 6, wherein said array of non-volatile memory cells are of the NAND type.

11. The non-volatile memory of claim 6, wherein said array of non-volatile memory operates as multi-state memory.

12. The non-volatile memory of claim 11, wherein selected portions of said array of non-volatile memory operates as binary memory.