System and apparatus for transmitting phase information from a client to a host between read and write operations

• US 8,301,930 B2
• Filed: 01/21/2009
• Issued: 10/30/2012
• Est. Priority Date: 09/19/2005
• Status: Active Grant

• Current Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Morein, Stephen, Macri, Joseph, Gauthier, Claude, Lee, Ming-Ju E., Chen, Lin
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Application Number:
  US12/356,804
• Publication Number:
  US 20090125747A1
• Time in Patent Office: 1,378 Days
• Field of Search: 713/400, 713/600, 713/503, 711/100
• US Class Current: 713/400
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Claims

1. A system, comprising:

a client device configured to transmit data to a host device, receive data from a host device, determine client clock phase information between a local client clock signal generated from a system timing signal and data received from the host device, and transmit client clock phase information to the host device during an electrical turnaround time between read and write operations over a data bus coupling the client device and the host device; and

a host device configured to receive the client clock phase information from the client device, the host device comprising shared data synchronization resources that use the client clock phase information to adjust a host clock for transmitting data to the at least one client device, wherein the shared resources are shared between transmit and receive functions of the host device.

2. The system of claim 1, wherein said host device further comprises a shared phased interpolator that adjusts a host clock based at least on the client clock phase information.

3. A phase detector for receiving data on a data link and for receiving a local clock signal during an electrical turnaround time between read and write operations over a data bus coupling a client device and a host device, said detector comprising:

a sampler that detects the relationship between the local clock signal and the received data and generates a phase information signal indicative of said detected relationship;

a logic unit for encoding the phase information signal as clock phase information; and

a transmitter that transmits the clock phase information,

wherein the clock phase information enables adjusting a host clock for transmitting data to at least one client device.

4. The detector of claim 3, wherein said phase information signal is a two bit encoded signal.

5. The detector of claim 3, wherein said logic identifies the local clock signal as one of early, late and aligned.

6. The detector of claim 3, wherein said logic is suitable for controlling a shared phase interpolator, which interpolator adjusts a local host clock.

7. The detector of claim 3, wherein said logic comprises phase control logic.

8. The detector of claim 3, wherein said detected relationship is a phase relationship.

9. The detector of claim 3, wherein the local clock signal is detected using an active edge.

10. The detector of claim 3, wherein the data is detected using a data eye.

11. The detector of claim 3, wherein the determined logic is transmitted during periods when the data link is not in use.

12. A host device for correcting a phase relationship determined at a client device between received data of the client device on a data link and a local clock signal of the client device, said host device comprising:

a receiver that receives logic during an electrical turnaround time between read and write operations over a data bus coupling the client device and the host device, wherein said received logic is determined from a phase information signal derived at the client device by comparing the phase relationship of a system timing signal generated local client clock signal and data received from the host device, wherein the phase information signal is indicative of the relationship between the client device local clock signal and client device received data; and

a synchronizer that determines an offset from the received logic and adjusts a host clock signal relative to said determined offset.

13. The device of claim 12, wherein the logic identifies the local client clock signal as one of early, late and aligned.

14. The device of claim 12, wherein said logic comprises phase control logic.

15. The device of claim 12, wherein said detected relationship is a phase relationship.

16. The device of claim 12, wherein the client device received data is detected using the data eye.

17. The device of claim 12, wherein the logic is received during periods when the data link is not in use.