Decompressors for low power decompression of test patterns

• US 8,301,945 B2
• Filed: 09/02/2011
• Issued: 10/30/2012
• Est. Priority Date: 07/21/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Rajski, Janusz, Mrugalski, Grzegorz, Czysz, Dariusz, Tyszer, Jerzy
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US13/225,240
• Publication Number:
  US 20110320999A1
• Time in Patent Office: 424 Days
• Field of Search: 714/726, 714/728, 714/729, 714/738, 714/733, 714/734
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Claims

1. An apparatus, comprising:

a linear finite state machine (LFSM) having two or more LFSM outputs and one or more LFSM inputs;

a register comprising two or more register inputs and two or more register outputs, the two or more register inputs being respectively coupled to the two or more LFSM outputs; and

a phase shifter comprising two or more phase shifter inputs and two or more phase shifter outputs, the two or more phase shifter inputs being respectively coupled to the two or more register outputs.

2. The apparatus of claim 1, further comprising a control channel coupled to a clock input of the register.

3. The apparatus of claim 2, wherein the control channel is coupled to the clock input of the shadow register via a logic gate.

4. The apparatus of claim 3, wherein the logic gate is an AND gate.

5. The apparatus of claim 2, wherein the control channel receives input from a single pin of the circuit-under-test.

6. The apparatus of claim 2, wherein the control channel is coupled to one or more logic gates, the logic gates being coupled to one or more test data inputs of the circuit-under-test.

7. The apparatus of claim 1, wherein the logic gates form an XOR network.

8. The apparatus of claim 1, wherein the LFSM is a linear feedback shift register (LFSR) or a ring generator.

9. The apparatus of claim 1, wherein the register is a first register, the apparatus further comprising a second register comprising two or more second register inputs and two or more second register outputs, the two or more second register inputs being respectively coupled to two or more additional LFSM outputs, and the two or more second register outputs being respectively coupled to two or more additional phase shifter inputs.

10. The apparatus of claim 1, wherein the register is a first register and the phase shifter is a first phase shifter, the apparatus further comprising:

a second register comprising two or more second register inputs and two or more second register outputs, the two or more second register inputs being respectively coupled to two or more additional LFSM outputs; and

a second phase shifter comprising two or more second phase shifter inputs and two or more second phase shifter outputs, the two or more second phase shifter inputs being respectively coupled to the two or more second register outputs.

11. One or more non-transitory computer-readable storage devices storing design data for implementing an apparatus, the apparatus comprising:

a linear finite state machine (LFSM) having two or more LFSM outputs and one or more LFSM inputs;

a register comprising two or more register inputs and two or more register outputs, the two or more register inputs being respectively coupled to the two or more LFSM outputs; and

a phase shifter comprising two or more phase shifter inputs and two or more phase shifter outputs, the two or more phase shifter inputs being respectively coupled to the two or more register outputs.

12. The one or more non-transitory computer-readable storage devices of claim 11, wherein the circuit design information further defines a control channel coupled to a clock input of the register.

13. The one or more non-transitory computer-readable storage devices of claim 11, wherein the logic gates form an XOR network.

14. The one or more non-transitory computer-readable storage devices of claim 11, wherein the LFSM is a linear feedback shift register (LFSR) or a ring generator.

15. The one or more non-transitory computer-readable storage devices of claim 11, wherein the register is a first register, and wherein the circuit design information further defines a second register comprising two or more second register inputs and two or more second register outputs, the two or more second register inputs being respectively coupled to two or more additional LFSM outputs, and the two or more second register outputs being respectively coupled to two or more additional phase shifter inputs.

16. One or more non-transitory computer-readable storage devices storing computer-executable instructions which when executed will cause a computer system to perform a method, the method comprising:

generating circuit design information for decompression circuitry, the circuit design information defining;

a linear finite state machine (LFSM) having two or more LFSM outputs and one or more LFSM inputs;

a register comprising two or more register inputs and two or more register outputs, the two or more register inputs being respectively coupled to the two or more LFSM outputs; and

a phase shifter comprising two or more phase shifter inputs and two or more phase shifter outputs, the two or more phase shifter inputs being respectively coupled to the two or more register outputs.

17. The one or more non-transitory computer-readable storage devices of claim 16, wherein the control channel is coupled to the clock input of the shadow register via a logic gate.

18. The one or more non-transitory computer-readable storage devices of claim 16, wherein the control channel is configured to receive input from a single pin.

19. The one or more non-transitory computer-readable storage devices of claim 16, wherein the control channel is coupled to one or more logic gates, the logic gates being coupled to one or more test data inputs of the circuit-under-test.

20. The one or more non-transitory computer-readable storage devices of claim 16, wherein the register is a first register and the phase shifter is a first phase shifter, and wherein the circuit design information further defines:

a second register comprising two or more second register inputs and two or more second register outputs, the two or more second register inputs being respectively coupled to two or more additional LFSM outputs; and

a second phase shifter comprising two or more second phase shifter inputs and two or more second phase shifter outputs, the two or more second phase shifter inputs being respectively coupled to the two or more second register outputs.