LDPC (low density parity check) coded modulation symbol decoding

• US 8,301,991 B2
• Filed: 11/30/2010
• Issued: 10/30/2012
• Est. Priority Date: 06/13/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian
• Primary Examiner(s): Chase, Shelly A
• Application Number:
  US12/957,238
• Publication Number:
  US 20110072336A1
• Time in Patent Office: 700 Days
• Field of Search: 714/752, 714/758, 714800-801
• US Class Current: 714/800
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/1117 using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
• CPC Class Codes: H03M 13/112 with correction functions for the min-sum rule, e.g. using an offset or a scaling factor
• CPC Class Codes: H03M 13/25 Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] modulation codes H03M13/31
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/4161 implementing path management
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/6516 Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
• CPC Class Codes: H03M 13/6583 Normalization other than scaling, e.g. by subtraction
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/1671 the supervisory signal being transmitted together with control information
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/2602 Signal structure

Abstract

LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.

Claims

1. An apparatus, comprising:

an input for receiving a signal including at least one symbol encoded therein, the at least one symbol including at least one uncoded bit; and

an LDPC (Low Density Parity Check) decoder for performing decoding of the signal, in accordance with symbol-based decoding using symbol metrics, thereby generating an estimate of the at least one symbol including an estimate of the at least one uncoded bit.

2. The apparatus of claim 1, wherein the LDPC decoder further comprising:

a symbol sequence estimate and symbol node update block for employing an updated edge message in accordance generating the estimate of the at least one uncoded bit; and

wherein;

the edge message corresponds to an edge that connects a check node and a symbol node within an LDPC coded modulation bipartite graph.

3. The apparatus of claim 2, wherein the LDPC decoder further comprising:

a check node update block for generating the updated edge message corresponding to the edge that connects the check node and the symbol node within the LDPC coded modulation bipartite graph.

4. The apparatus of claim 1, wherein:

the at least one symbol being a first symbol within the signal;

a second symbol within the signal not including any uncoded bits; and

the LDPC decoder performing decoding of the signal thereby generating an estimate of the second symbol.

5. The apparatus of claim 1, wherein:

the at least one symbol being a first symbol within the signal including a first plurality of bits; and

a second symbol within the signal including a second plurality of bits, the second plurality of bits having a different number of bits than the first plurality of bits.

6. The apparatus of claim 1, wherein:

the at least one symbol being a first symbol within the signal mapped to a first constellation whose constellation points are mapped according to a first mapping; and

a second symbol within the signal being mapped to a second constellation whose constellation points are mapped according to a second mapping.

7. The apparatus of claim 1, wherein:

the at least one symbol being a first symbol within the signal mapped to a constellation when its constellation points are mapped according to a first mapping; and

a second symbol within the signal being mapped to the constellation when its constellation points are mapped according to a second mapping.

8. The apparatus of claim 1, wherein:

the at least one symbol being a first symbol within the signal having a first code rate; and

a second first symbol within the LDPC coded signal has a second code rate.

9. The apparatus of claim 1, wherein the LDPC decoder:

decomposing the estimate of the at least one symbol into a plurality of soft bit estimates corresponding to respective bits within the at least one symbol; and

employing the plurality of soft bit estimates in accordance with making a plurality of hard bit estimates corresponding to the respective bits within the at least one symbol.

10. The apparatus of claim 1, wherein:

the apparatus being a communication device; and

the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, a fiber-optic communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.

11. An apparatus, comprising:

an input for receiving a signal including at least one symbol encoded therein, the at least one symbol including at least one uncoded bit; and

an LDPC (Low Density Parity Check) decoder for performing decoding of the signal in accordance with symbol-based decoding using symbol metrics, the LDPC decoder including;

a check node update block for generating an updated edge message corresponding to an edge connecting a check node and a symbol node within an LDPC coded modulation bipartite graph;

a symbol sequence estimate and symbol node update block for employing the updated edge message in accordance generating an estimate of the at least one symbol including an estimate of the at least one uncoded bit.

12. The apparatus of claim 11, wherein:

the at least one symbol being a first symbol within the signal including a first plurality of bits; and

a second symbol within the signal including a second plurality of bits, the second plurality of bits having a different number of bits than the first plurality of bits.

13. The apparatus of claim 11, wherein the LDPC decoder:

decomposing the estimate of the at least one symbol into a plurality of soft bit estimates corresponding to respective bits within the at least one symbol; and

employing the plurality of soft bit estimates in accordance with making a plurality of hard bit estimates corresponding to the respective bits within the at least one symbol.

14. The apparatus of claim 11, wherein:

the apparatus being a communication device; and

the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, a fiber-optic communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.

15. A method for operating a communication device, the method comprising:

via an input of the communication device, receiving a signal including at least one symbol encoded therein, the at least one symbol including at least one uncoded bit; and

performing LDPC (Low Density Parity Check) decoding of the signal, in accordance with symbol-based decoding using symbol metrics, thereby generating an estimate of the at least one symbol including an estimate of the at least one uncoded bit.

16. The method of claim 15, further comprising:

operating a symbol sequence estimate and symbol node update block, within an LDPC decoder of the communication device, for employing an updated edge message in accordance generating the estimate of the at least one uncoded bit; and

wherein;

the edge message corresponds to an edge that connects a check node and a symbol node within an LDPC coded modulation bipartite graph.

17. The method of claim 16, further comprising:

operating a check node update block, within an LDPC decoder of the communication device, for generating the updated edge message corresponding to the edge that connects the check node and the symbol node within the LDPC coded modulation bipartite graph.

18. The method of claim 15, wherein:

the at least one symbol being a first symbol within the signal including a first plurality of bits; and

a second symbol within the signal including a second plurality of bits, the second plurality of bits having a different number of bits than the first plurality of bits.

19. The method of claim 15, further comprising:

decomposing the estimate of the at least one symbol into a plurality of soft bit estimates corresponding to respective bits within the at least one symbol; and

employing the plurality of soft bit estimates in accordance with making a plurality of hard bit estimates corresponding to the respective bits within the at least one symbol.

20. The method of claim 15, wherein:

the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, a fiber-optic communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.