Compact modeling of circuit stages for static timing analysis of integrated circuit designs

• US 8,302,046 B1
• Filed: 11/11/2008
• Issued: 10/30/2012
• Est. Priority Date: 11/11/2008
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Keller, Igor, Tam, King Ho
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US12/269,037
• Time in Patent Office: 1,449 Days
• Field of Search: 716/108
• US Class Current: 716/108
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

Systems, apparatus, and methods of timing analysis with a multi-operating region gate model are disclosed, including modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation; in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation; and, in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation. Instantaneous output current provided by the time varying voltage dependent current source in the VCR region is responsive to time and the instantaneous output voltage of the logic gate. Instantaneous output current provided by the time-invariant voltage dependent current source in the AR region is responsive to the instantaneous output voltage of the logic gate.

Claims

1. A system for analysis of an integrated circuit design, the system comprising:

a processor to execute instructions to perform operations in analyzing timing of an integrated circuit design; and

a processor readable storage device to store instructions that when executed by the processor cause the processor to perform operations including

modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation;

in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation, wherein an instantaneous output current provided by the time varying voltage dependent current source is responsive to time and an instantaneous output voltage of the logic gate; and

in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation, wherein an instantaneous output current provided by the time-invariant voltage dependent current source is responsive to instantaneous output voltage of the logic gate independent of time.

2. The system of claim 1, wherein

output current of the logic gate in the steady state region of operation is substantially zero.

3. The system of claim 1, wherein

the transition from the steady state region of operation occurs at an offset time when the instantaneous output voltage of the logic gate starts to change from a steady state voltage level in response to an input voltage transition at an input pin of the logic gate.

4. The system of claim 1, wherein

an input pin of the logic gate is at a first steady state level in the steady state region of operation;

and

the transition from the varying current region of operation occurs at a cutoff time when the instantaneous output voltage and current of the logic gate begins to behave asymptotically with respect to time.

5. The system of claim 4, wherein

the cutoff time is responsive to the input slew rate of the input voltage transition at the input pin.

6. The system of claim 4, wherein

the cutoff time is after an input voltage transition at an input pin of the logic gate reaches a second steady state level.

7. The system of claim 1, wherein

an output voltage response of the logic gate in the asymptotic region of operation is an asymptotic transition with respect to time.

8. A non-transitory machine readable product for timing analysis of an integrated circuit design, the non-transitory machine readable product comprising:

a machine readable storage device having stored therein machine readable instructions

to model a logic gate with different current source models for a steady state region of operation, a varying current region of operation, and an asymptotic region of operation;

in response to a transition at an input of the logic gate, to determine instantaneous output current for the varying current region of operation in response to time and an instantaneous output voltage of the logic gate, and

in response to the transition at the input of the logic gate, to determine instantaneous output current for the asymptotic region of operation in response to the instantaneous output voltage of the logic gate independent of time.

9. The non-transitory machine readable product of claim 8, wherein

the current source model for the steady state region of operation is an open circuit,

the current source model for the varying current region of operation is a time varying voltage dependent current source, and

the current source model for the asymptotic region of operation is a time-invariant voltage dependent current source.

10. The non-transitory machine readable product of claim 8, wherein

a boundary between the steady state region of operation and the varying current region of operation is reached at an offset time when the instantaneous output voltage of the logic gate starts to change from a steady state voltage level in response to the input voltage transition at the input pin of the logic gate, and

a boundary between the varying current region of operation and the asymptotic region of operation is reached at a cutoff time when the instantaneous output voltage and the instantaneous output current of the logic gate begins to behave asymptotically with respect to time.

11. The non-transitory machine readable product of claim 9, wherein

a terminal of the open circuit has a constant voltage for the steady state region of operation.

12. A method for analyzing timing of an integrated circuit design, the method comprising:

with a processor

modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation;

in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation, wherein an instantaneous output current provided by the time varying voltage dependent current source is responsive to time and an instantaneous output voltage of the logic gate; and

in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation, wherein an instantaneous output current provided by the time-invariant voltage dependent current source is responsive to the instantaneous output voltage of the logic gate independent of time.

13. The method of claim 12, wherein

output current of the logic gate in the steady state region of operation is substantially zero.

14. The method of claim 12, wherein

the transition from the steady state region of operation occurs at an offset time when the instantaneous output voltage of the logic gate starts to change from a steady state voltage level in response to an input voltage transition at an input pin of the logic gate.

15. The method of claim 12, wherein

an input pin of the logic gate is at a first steady state level in the steady state region of operation;

and

the transition from the varying current region of operation occurs at a cutoff time when the instantaneous output voltage and current of the logic gate begins to behave asymptotically with respect to time.

16. The method of claim 15, wherein

the cutoff time is responsive to the input slew rate of the input voltage transition at the input pin.

17. The method of claim 15, wherein

the cutoff time is after an input voltage transition at an input pin of the logic gate reaches a second steady state level.

18. The method of claim 12, wherein

an output voltage response of the logic gate in the asymptotic region of operation is an asymptotic transition with respect to time.