Aware manufacturing of an integrated circuit

• US 8,302,061 B2
• Filed: 08/29/2011
• Issued: 10/30/2012
• Est. Priority Date: 05/20/2005
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Fujimura, Akira, Scheffer, Louis K.
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US13/220,678
• Publication Number:
  US 20110314436A1
• Time in Patent Office: 428 Days
• Field of Search: 716/110, 716/126, 716/129, 716/130, 716/132, 716/136
• US Class Current: 716/126
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091

Abstract

Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC based on the designed IC layout. Some embodiments concurrently select an optimal pair of wiring and illumination configurations. Other embodiments select an illumination configuration based on the selected wiring configuration. Yet other embodiments select a wiring configuration based on the selected illumination configuration. In some embodiments, selecting the illumination configuration entails selecting at least one stepper lens for the IC layout, where the stepper lens illuminates at least one mask for at least one particular layer of the IC layout. In some embodiments, this selection entails selecting a stepper lens for each particular layer of the IC layout. Also, in some embodiments, selecting the wiring configuration entails defining the width and/or spacing of the routes along different directions on at least one particular wiring layer of the IC layout. In some embodiments, this selection entails selecting width and/or spacing of routes along different directions on each particular layer of the IC layout.

Claims

1. A design aware process for manufacturing an integrated circuit (“

IC”

), the process comprising;

identifying dimensional attributes of a plurality of routes for an IC layout by identifying (i) a first minimum width for each route in the plurality of routes along a first direction in a first region of a first layer of the IC layout and (ii) a second minimum width for each route in the plurality of routes along the first direction in a second region of the first layer of the IC layout;

selecting an illumination configuration based on the dimensional attributes comprising the first and second minimum widths identified along the first direction;

designing the IC layout comprising a set of routes having said first and second minimum widths along the first direction; and

using the selected illumination configuration to manufacture the IC based on the designed IC layout.

2. The process of claim 1, wherein identifying dimensional attributes of the plurality of routes further comprises identifying a third width for each route in the plurality of routes along a second direction of the first layer of the IC layout.

3. The process of claim 1, wherein the first minimum width is narrower than the second minimum width.

4. The process of claim 1, wherein selecting the illumination configuration comprises selecting a dipole lens for each of the first and second regions of the first layer of the IC layout.

5. The process of claim 4, wherein the first direction is a vertical direction, wherein each dipole lens includes horizontally aligned poles.

6. The process of claim 4, wherein the first direction is a horizontal direction, wherein each dipole lens includes vertically aligned poles.

7. The process of claim 4, wherein the first direction a 45°

diagonal direction, wherein each dipole lens includes 135°

aligned poles.

8. The process of claim 4, wherein the first direction is a 135°

diagonal direction, wherein each dipole lens includes 45°

aligned poles.

9. A non-transitory computer readable medium storing a computer program which when executed by at least one processor manufactures an integrated circuit (“

IC”

), the computer program comprising sets of instructions for;

identifying dimensional attributes of a plurality of routes for an IC layout by identifying (i) a first minimum width for each route in the plurality of routes along a first direction in a first region of a first layer of the IC layout, (ii) a second minimum width for each route in the plurality of routes along the first direction in a second region of the first layer of the IC layout, and (iii) a third width for each route in the plurality of routes along a second diagonal direction of the first layer of the IC layout, wherein the first minimum width and the second minimum width are narrower than the third width;

selecting an illumination configuration based on the dimensional attributes comprising the first and second minimum widths identified along the first direction and the third width identified along the second diagonal direction;

designing the IC layout comprising set of routes having said first and second minimum widths along the first direction and the third width along the second diagonal direction; and

using the selected illumination configuration to manufacture the IC based on the designed IC layout.

10. The non-transitory computer readable medium of claim 9, wherein the first direction is a non-diagonal direction, wherein the set of instructions for selecting the illumination configuration comprises a set of instructions for selecting a quadrupole lens for the first layer of the IC layout.

11. The non-transitory computer readable medium of claim 9, wherein the set of instructions for using the selected illumination configuration to manufacture the IC based on the designed IC layout comprises a set of instructions for automatically using the selected illumination configuration.

12. The non-transitory computer readable medium of claim 9, wherein the set of instructions for using the selected illumination configuration to manufacture the IC based on the designed IC layout comprises manually using the selected illumination configuration.

13. A system for design aware manufacturing of an integrated circuit (“

IC”

), the system comprising;

at least one processor for executing sets of instructions; and

a memory storing a computer program for manufacturing an IC, the computer program comprising sets of instructions to be executed in the processor for;

identifying dimensional attributes of a plurality of routes for an IC layout by identifying (i) a first minimum width for each route in the plurality of routes along a first diagonal direction in a first region of a first layer of the IC layout and (ii) a second minimum width for each route in the plurality of routes along the first diagonal direction in a second region of the first layer of the IC layout;

based on the dimensional attributes comprising the first and second minimum widths identified along the first diagonal direction, selecting an illumination configuration by selecting a dipole lens for each of the first and second regions of the first layer of the IC layout, wherein each dipole lens includes diagonally aligned poles;

designing the IC layout comprising a set of routes having said first and second minimum widths along the first diagonal direction; and

using the selected illumination configuration to manufacture the IC based on the designed IC layout.

14. The system of claim 13, wherein the set of instructions for identifying dimensional attributes of the plurality of routes further comprises a set of instructions for identifying a third width for each route in the plurality of routes along a second direction of the first layer of the IC layout.

15. The system of claim 13, wherein the set of instructions for identifying dimensional attributes of the plurality of routes further comprises sets of instructions for:

identifying a first width for each route in the plurality of routes along the first diagonal direction of a second layer of the IC layout; and

identifying a second width for each route in the plurality of routes along a second direction of the second layer of the IC layout.

16. The system of claim 15, wherein the set of instructions for selecting the illumination configuration based on the dimensional attributes comprises a set of instructions for selecting a stepper lens for the second layer of the IC layout.

17. The system of the claim 13, wherein the computer program further comprises a set of instructions for identifying a first spacing constraint for routes in the first region and a second spacing constraint for routes in the second region.

18. The system of claim 13, wherein the first diagonal direction is a 45°

direction, wherein each dipole lens includes 135°

aligned poles.

19. The system of claim 13, wherein the first diagonal direction is a 135°

direction, wherein each dipole lens includes 45°

aligned poles.