Methods and apparatus to provide a managed runtime environment in a sequestered partition

• US 8,302,082 B2
• Filed: 06/07/2006
• Issued: 10/30/2012
• Est. Priority Date: 06/07/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zimmer, Vincent J., Rothman, Michael A.
• Primary Examiner(s): DAO, THUY CHAN
• Application Number:
  US11/422,763
• Publication Number:
  US 20070288912A1
• Time in Patent Office: 2,337 Days
• Field of Search: None
• US Class Current: 717/140
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/45516 Runtime code conversion or optimisation
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals

Abstract

Apparatus and methods of managed runtime in an embedded partition are disclosed. An example processor system has a general partition having a central processing unit (CPU) to run a first operating system. An embedded partition has a second central processing unit (CPU) to run a second operating system. An inter-partition bridge exchanges an instruction between the general partition and the embedded partition. The first operating system includes a managed runtime environment filter to evaluate the instruction and determine whether the embedded partition can process the instruction.

Claims

1. A processor system, comprising:

a general partition having a central processing unit (CPU), the general partition including a load monitor to receive an instruction;

an embedded partition having a second CPU;

an inter-partition bridge (IPB) in communication with the general partition and the embedded partition to pass an instruction from the general partition to the embedded partition;

a thread scheduler to create a raw thread context (RTC) frame from the instruction and to translate the RTC frame into a bytecode-oriented thread context (BTC) for transmission to the embedded partition via the IPB;

a managed runtime environment filter to evaluate the instruction and pass the instruction via the IPB when the embedded partition can process the instruction; and

an operating system executing on the general partition to determine whether an acceleration application is enabled on the embedded partition, to invoke the embedded partition to compile the instruction when the acceleration application is enabled on the embedded partition, and to initiate execution of the instruction on the general partition when the acceleration application is not enabled.

2. The processor system of claim 1 wherein the IPB is a shared memory accessible by the general partition and the embedded partition.

3. The processor system of claim 1 wherein the IPB is a hardware input/output controller accessible by the general partition and the embedded partition.

4. The processor system of claim 1 wherein the second CPU of the embedded partition is to improve execution of a function.

5. The processor system of claim 4 wherein the function is just in time compilation.

6. The processor system of claim 1 further comprising a memory accessible by the embedded partition, the memory storing an application comprising one of a Java virtual machine or a common language run time (CLR) intermedial language compiler.

7. The processor system of claim 1 wherein the instruction is one of an XML instruction, a CLR intermedial instruction, or a Java instruction.

8. The processor system of claim 1

further comprising a migration manager to restore the RTC frame from the BTC.

9. The processor system of claim 1 further comprising:

a first hardware device exclusively controllable by a first OS on the general partition; and

a second hardware device exclusively controllable by a second OS on the embedded partition.

10. A tangible machine readable storage medium comprising instructions which, when executed, cause a processor system to, at least:

run a first operating system executing on a general partition to read an instruction;

create a raw thread context (RTC) frame from the instruction;

identify whether an embedded partition includes an enabled acceleration application that can process the instruction;

translate the RTC into a bytecode-oriented thread context (BTC) for transmission to the embedded partition;

transmit the instruction via an inter-partition bridge to the embedded partition in response to identifying the enabled acceleration application;

process the instruction with the embedded partition with a second operating system when the acceleration application is enabled; and

process the instruction with the first operating system with the general partition when the acceleration application is not enabled.

11. The machine readable storage medium of claim 10 which when executed further causes the processor system to process the instruction using just in time compilation.

12. The machine readable storage medium of claim 10 wherein the second operating system is to run an application to process the instruction, the application comprising at least one of a Java virtual machine or a common language run time (CLR) intermedial language compiler.

13. The machine readable storage medium of claim 10 wherein the instruction is at least one of an XML instruction, a CLR intermedial language instruction, or a Java instruction.

14. The machine readable storage medium of claim 10 storing instructions which, when executed, cause a processor system to

restore the RTC from the BTC in the embedded partition.