Inverter manufacturing method and inverter

• US 8,304,298 B2
• Filed: 05/15/2008
• Issued: 11/06/2012
• Est. Priority Date: 05/18/2007
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Ofuji, Masato, Abe, Katsumi, Hayashi, Ryo, Sano, Masafumi, Kumomi, Hideya
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US12/597,211
• Publication Number:
  US 20100085081A1
• Time in Patent Office: 1,636 Days
• Field of Search: 438/149, 438/104, 438/275, 438/795, 257/E21.698
• US Class Current: 438/149
• CPC Class Codes: H01L 27/1233 with different thicknesses of the active layer in different devices
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

To provide an enhancement-depletion (E/D) inverter which can be easily manufactured, in the present invention, a method of manufacturing an inverter which is composed of an oxide semiconductor in which a channel layer includes at least one element selected from In, Ga and Zn formed on a same substrate, the inverter being the E/D inverter having plural thin film transistors, is characterized by comprising the steps of: forming a first transistor and a second transistor, the thicknesses of the channel layers of the first and second transistors being mutually different; and executing heat treatment to at least one of the channel layers of the first and second transistors.

Claims

1. A method of manufacturing an enhancement-depletion (E/D) inverter, the method comprising the steps of:

forming a first transistor and a second transistor over a substrate, the first transistor and the second transistor each comprising a channel layer comprising an oxide semiconductor including at least one element selected from In, Ga and Zn, and thicknesses of the channel layers of the first and second transistors being different from each other; and

performing heat treatment on at least one of the channel layers of the first and second transistors,

wherein the first transistor and the second transistor are included in the enhancement-depletion inverter.

2. A method according to claim 1, wherein, in said step of performing heat treatment, the heat treatment is executed by applying more heat to either one of the channel layer of the first transistor and the channel layer of the second transistor.

3. A method according to claim 1, wherein said step of performing heat treatment includes the step of locally heating a partial region of the channel layer by contact heating or by irradiation with electromagnetic waves.

4. A method according to claim 1, wherein the inverter is formed such that the inverter has at least one of

a construction in which a constituent material of a source electrode of the first transistor and a constituent material of a source electrode of the second transistor are different from each other,

a construction in which a constituent material of a drain electrode of the first transistor and a constituent material of a drain electrode of the second transistor are different from each other, and

a construction in which a constituent material of a gate electrode of the first transistor and a constituent material of a gate electrode of the second transistor are different from each other, and

said step of performing heat treatment includes the step of heating the channel layer by irradiation of electromagnetic waves.

5. A method according to claim 4, wherein the inverter has at least one kind of

a construction in which a property of the constituent material of the source electrode of the first transistor and a property of the constituent material of the source electrode of the second transistor are different from each other,

a construction in which a property of the constituent material of the drain electrode of the first transistor and a property of the constituent material of the drain electrode of the second transistor are different from each other, and

a construction in which a property of the constituent material of the gate electrode of the first transistor and a property of the constituent material of the gate electrode of the second transistor are different from each other, and

the property is at least one selected from resistivity, specific heat and absorption coefficient.

6. A method according to claim 1, further comprising the step of executing etching of the channel layers in order to make the thicknesses of the channel layers of the first and second transistors different from each other.

7. A method according to claim 1, wherein, in order to make the thicknesses of the channel layers of the first and second transistors different from each other, the number of time(s) of performing said step of depositing the channel layer of the first transistor is made different from the number of time(s) of performing said step of depositing the channel layer of the second transistor.

8. A method of manufacturing an enhancement-depletion (E/D) inverter, the method comprising the steps of:

forming a common deposition film over a substrate, acting as the channel layer of a first transistor and the channel layer of a second transistor, the channel layer of the first transistor and the channel layer of the second transistor each comprising an oxide semiconductor including at least one element selected from In, Ga and Zn; and

performing heat treatment by applying a larger heating value to either one of the channel layer of the first transistor and the channel layer of the second transistor,

wherein the first transistor and the second transistor are included in the enhancement-depletion inverter.

9. A method according to claim 8, wherein said step of performing heat treatment includes the step of locally heating a partial region of the channel layer by contact heating or by irradiation with electromagnetic waves.

10. A method according to claim 8, wherein the inverter has at least one of

a construction in which a constituent material of a source electrode of the first transistor and a constituent material of a source electrode of the second transistor are different from each other,

a construction in which a constituent material of a drain electrode of the first transistor and a constituent material of a drain electrode of the second transistor are different from each other, and

a construction in which a constituent material of a gate electrode of the first transistor and a constituent material of a gate electrode of the second transistor are different from each other, and

said step of performing heat treatment includes the step of heating the channel layer by irradiation with electromagnetic waves.

11. A method according to claim 10, wherein the inverter has at least one of

a construction in which a property of the constituent material of the source electrode of the first transistor and a property of the constituent material of the source electrode of the second transistor are different from each other,

a construction in which a property of the constituent material of the drain electrode of the first transistor and a property of the constituent material of the drain electrode of the second transistor are different from each other, and

a construction in which a property of the constituent material of the gate electrode of the first transistor and a property of the constituent material of the gate electrode of the second transistor are different from each other, and

the property is at least one selected from resistivity, specific heat and absorption coefficient.

12. An enhancement-depletion inverter comprising a first oxide semiconductor thin film transistor and a second oxide semiconductor thin film transistor which are formed over a substrate, wherein each of the first oxide semiconductor thin film transistor and the second oxide semiconductor transistor includes at least one element selected from In, Ga and Zn,

wherein thicknesses of channel layers of the first oxide semiconductor transistor and the second oxide semiconductor transistor are different from each other,

wherein threshold voltages of the first oxide semiconductor transistor and the second oxide semiconductor transistor are different from each other, and

wherein said first and second oxide semiconductor transistors are structured to operate as at least part of said enhancement-depletion inverter.

13. The enhancement-depletion inverter according to claim 12, wherein said enhancement-depletion inverter is constructed to operate if a power supply voltage which satisfies a condition that a difference between the threshold voltages of the two transistors is 70% or more and 200% or less of the power supply voltage is supplied.

14. The enhancement-depletion inverter according to claim 12, wherein the enhancement-depletion inverter has at least one of:

a construction in which a constituent material of a source electrode of the first oxide semiconductor transistor and a constituent material of a source electrode of the second oxide semiconductor transistor are different from each other;

a construction in which a constituent material of a drain electrode of the first oxide semiconductor transistor and a constituent material of a drain electrode of the second oxide semiconductor transistor are different from each other; and

a construction in which a constituent material of a gate electrode of the first oxide semiconductor transistor and a constituent material of a gate electrode of the second oxide semiconductor transistor are different from each other.

15. The enhancement-depletion inverter according to claim 12, wherein the inverter has at least one of:

a construction in which a property of a constituent material of a source electrode of the first oxide semiconductor transistor and a property of a constituent material of a source electrode of the second oxide semiconductor transistor are different from each other,

a construction in which a property of a constituent material of a drain electrode of the first oxide semiconductor transistor and a property of a constituent material of a drain electrode of the second oxide semiconductor transistor are different from each other, and

a construction in which a property of a constituent material of a gate electrode of the first oxide semiconductor transistor and a property of a constituent material of a gate electrode of the second oxide semiconductor transistor are different from each other.