Fabrication of devices having different interfacial oxide thickness via lateral oxidation

• US 8,304,306 B2
• Filed: 03/28/2011
• Issued: 11/06/2012
• Est. Priority Date: 03/28/2011
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Cai, Jin, Cartier, Eduard A., Frank, Martin M., Khater, Marwan H.
• Primary Examiner(s): AU, BAC H
• Application Number:
  US13/073,110
• Publication Number:
  US 20120248537A1
• Time in Patent Office: 589 Days
• Field of Search: 438/199, 438/213, 438/216, 438/261, 438/275, 438/279, 438/283, 438/287, 438/591
• US Class Current: 438/216
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method for forming a semiconductor device includes forming a first field effect transistor (FET) and a second FET on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer; encapsulating the first interfacial oxide layer of the first FET; and performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the lateral oxidation of the second interfacial oxide layer of the second FET converts a portion of the substrate located underneath the second FET into additional interfacial oxide.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming a first field effect transistor (FET) and a second FET on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer;

encapsulating the first interfacial oxide layer of the first FET; and

performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the lateral oxidation of the second interfacial oxide layer of the second FET converts a portion of the substrate located underneath the second FET into additional interfacial oxide.

2. The method of claim 1, wherein the first and second interfacial oxide layers comprise one of silicon oxide and silicon oxynitride.

3. The method of claim 1, wherein the substrate comprises one of silicon and silicon germanium.

4. The method of claim 1, wherein the lateral oxidation is performed at a temperature from about 400°

C. to about 800°

C.

5. The method of claim 4, wherein the lateral oxidation is performed at a temperature of about 700°

C.

6. The method of claim 1, wherein the lateral oxidation is performed for a lateral oxidation time period that is determined based on a gate length of the second FET.

7. The method of claim 1, wherein encapsulating the first interfacial oxide layer of the first FET comprises depositing an oxidation-resistant material over the first FET.

8. The method of claim 7, wherein the oxidation-resistant material comprises silicon nitride.

9. The method of claim 1, further comprising:

forming an oxide liner over the first FET and the second FET;

removing the oxide liner from the first FET;

forming first oxidation-resistant material over the first FET, wherein forming the first oxidation-resistant material over the first FET comprises encapsulating the first interfacial oxide layer of the first FET, and forming second oxidation-resistant material over the oxide liner on the second FET; and

removing a portion of the oxide liner from the second FET to expose the second interfacial oxide layer of the second FET.

10. The method of claim 1, wherein the lateral oxidation of the second interfacial oxide layer of the second FET further converts a portion of the substrate located adjacent to the second FET in the substrate into excess oxide.

11. The method of claim 10, further comprising removing the excess oxide from the substrate after the lateral oxidation to form a recess in the substrate adjacent to the second FET.

12. The method of claim 11, further comprising forming gate and source/drain silicide for the first and second FETs after performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the source/drain silicide for the second FET is formed in the recess in the substrate adjacent to the second FET.

13. The method of claim 1, wherein the first FET comprises the first interfacial oxide layer located on the substrate, a first high-k dielectric layer located on the first interfacial oxide layer, and a first gate metal layer located on the first high-k dielectric layer;

and

wherein the second FET comprises the second interfacial oxide layer located on the substrate, a second high-k dielectric layer located on the second interfacial oxide layer, and a second gate metal layer located on the second high-k dielectric layer.

14. The method of claim 13, wherein the first FET further comprises a first gate silicon layer located over the first gate metal layer, and the second FET further comprises a second gate silicon layer located over the second gate metal layer, and further comprising:

siliciding the first and second gate silicon layers after performing lateral oxidation of the second interfacial oxide layer of the second FET.