Charged balanced devices with shielded gate trench

• US 8,304,312 B2
• Filed: 02/17/2011
• Issued: 11/06/2012
• Est. Priority Date: 08/20/2008
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hébert, François
• Primary Examiner(s): Menz, Laura
• Application Number:
  US12/932,172
• Publication Number:
  US 20110147836A1
• Time in Patent Office: 628 Days
• Field of Search: 438/268, 438/104, 438/259
• US Class Current: 438/268
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

Claims

1. A method for forming a semiconductor power device on a semiconductor substrate comprising:

providing a semiconductor substrate;

opening a plurality of deep, trenches in the semiconductor substrate and growing an epitaxial layer that fills said deep trenches and covers a top surface of said semiconductor substrate with a top epitaxial layer, wherein the portions of the epitaxial layer in the epitaxial deep trench and said top epitaxial layer are simultaneously grown as a single layer and wherein the epitaxial layer is of an opposite conductivity type as the semiconductor substrate; and

forming a plurality of trench MOSFET cells in said top epitaxial layer by opening a plurality of trench gates and implanting a plurality of gate-shielding dopant regions below said gate trenches for shielding trench gates of said transistor cells during a voltage breakdown of said semiconductor power device with the top epitaxial layer acting as the body region and the semiconductor substrate acting as the drain region, wherein a super junction effect is achieved through charge balance between the portions of the epitaxial layer in the deep trenches and the portions of the semiconductor substrate lateral to the deep trenches.

2. The method of claim 1 further comprising:

implanting through the sidewalls of the deep trenches with dopants of a first conductivity type to form a lateral concentration gradient in regions of said semiconductor substrate between said deep trenches and adjusting said device performance of said semiconductor power device by adjusting the deep trench sidewall implant.

3. The method of claim 1 wherein:

said step of implanting a plurality of gate-shielding dopant regions below said gate trenches further comprising a step of implanting said plurality of gate-shielding dopant regions at a distance below a bottom surface of said gate trenches wherein said gate shielding dopant regions having no contact with said trench gate.

4. The method of claim 1 further comprising:

implanting through the bottom of the gate trenches a dopant region of a same conductivity type as the substrate.

5. The method of claim 1 further comprising:

implanting the sidewalls and bottom of the gate trenches a dopant of a same conductivity type as the semiconductor substrate.

6. The method of claim 1 wherein:

said step of providing a semiconductor substrate includes a step of providing a single layer semiconductor substrate and wherein said step of opening a plurality of deep trenches comprises a step of opening a plurality of deep trenches in the single layer semiconductor substrate.

7. The method of claim 1 wherein:

said step of providing a semiconductor substrate further comprising a step of providing a heavily doped bottom substrate and growing a top substrate layer on top of the bottom substrate, wherein the top substrate layer is of a same conductivity type as the bottom substrate.

8. The method of claim 5 further comprising:

heavily doping the bottom of the deep trenches to form a drain contact region before said step of growing said epitaxial layer; and

backgrinding the substrate to expose the drain contact region.

9. The method of claim 1 further comprising:

performing a partial CMP to a top surface of the epitaxial layer to smooth the top surface before said step of forming said plurality of trench MOSFET cells.