Method of forming an MOS transistor

• US 8,304,314 B2
• Filed: 09/24/2008
• Issued: 11/06/2012
• Est. Priority Date: 09/24/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Pearse, Jeffrey, Venkatraman, Prasad, Sellers, James, Bhatt, Hemanshu D.
• Primary Examiner(s): Le, Dung A.
• Application Number:
  US12/236,718
• Publication Number:
  US 20100072544A1
• Time in Patent Office: 1,504 Days
• Field of Search: 438/197, 438/270, 257328-334
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a method of forming an MOS transistor includes forming the MOS transistor to have an active region and a termination region. Within the termination region the method includes forming a plurality of trenches having a conductor within the plurality of trenches. The method also includes forming another conductor to make electrical contact to one of the conductors within the plurality of trenches.

Claims

1. A method of forming an MOS transistor comprising:

providing a semiconductor substrate;

forming the MOS transistor on the semiconductor substrate including forming the MOS transistor with an active region and a termination region that is external to the active region;

forming an active trench in the active region;

forming a first trench and a second trench within the termination region;

forming a first conductor within the termination region and overlying the first trench wherein the first conductor is electrically connected to a second conductor within the first trench; and

forming the second conductor to electrically contact a third conductor that is within the active trench.

2. The method of claim 1 further including forming a fourth conductor in the termination region and overlying the second trench wherein the fourth conductor is electrically connected to a fifth conductor within, the second trench.

3. The method of claim 2 further including forming the fifth conductor electrically connected to a sixth conductor that is in the active trench.

4. The method of claim 2 wherein forming the fourth conductor includes forming the fourth conductor and the first conductor to be substantially coplanar wherein both the fourth conductor and the first conductor are overlying a surface of the semiconductor substrate.

5. The method of claim 2 wherein forming the fourth conductor includes forming the fourth conductor and the first conductor to be inter-digitated.

6. The method of claim 2 further including forming the second conductor electrically connected to a sixth conductor that is formed within the second trench.

13. The method of claim 1 further including forming the second trench within the termination region positioned near the first trench and the active trench including forming a third conductor within the second trench wherein no source region is adjacent to the second trench.

7. A method of forming a transistor comprising:

providing a semiconductor substrate having a surface;

forming a plurality first trenches in an active region of the transistor;

forming a second trench and a third trench extending into the semiconductor substrate including forming the second trench and the third trench in a termination region of the transistor that is not in the active region of the transistor;

forming a first conductor within the second trench;

forming a second conductor within the third trench;

forming a third conductor overlying the surface of the semiconductor substrate and overlying the second trench and electrically contacting the first conductor; and

forming the first conductor electrically connected to a fourth conductor within at least one trench of the plurality of first trenches.

8. The method of claim 7 wherein forming the second trench and the third trench extending into the semiconductor substrate includes forming a dielectric layer on the surface of the semiconductor substrate and forming the second trench and the third trench extending through the dielectric layer and into the semiconductor substrate.

9. The method of claim 8 wherein forming the dielectric layer on the surface of the semiconductor substrate includes forming the dielectric layer in the termination region but not in the active region.

10. The method of claim 7 further including forming a fifth conductor overlying the surface of the semiconductor substrate and overlying the third trench and electrically contacting the second conductor but not the first conductor.

11. The method of claim 10 wherein forming the fifth conductor includes forming the fifth conductor substantially coplanar with the third conductor.

12. The method of claim 11 wherein forming the second trench and the third trench extending into the semiconductor substrate includes forming a dielectric layer on the surface of the semiconductor substrate and forming the second trench and the third trench extending through the dielectric layer and into the semiconductor substrate and further including forming the third conductor and the fifth conductor on the dielectric layer.

14. The method of claim 7 wherein forming the third trench includes forming the third trench near the first trench wherein no source region is adjacent to the third trench.

15. The method of claim 7 wherein forming the plurality of first trenches includes forming the one trench of the plurality of first trenches to include a fifth conductor overlying the fourth conductor and electrically insulated from the fourth conductor.